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41. 发明申请

US20080173985A1 DIELECTRIC CAP HAVING MATERIAL WITH OPTICAL BAND GAP TO SUBSTANTIALLY BLOCK UV RADIATION DURING CURING TREATMENT, AND RELATED METHODS 审中-公开
标题翻译：具有光学带隙的材料的电介质板在固化处理期间实质性地阻挡紫外线辐射，以及相关方法
公开(公告)号：US20080173985A1
公开(公告)日：2008-07-24
申请号：US11626552
申请日：2007-01-24
申请人： Michael P. Belyansky , Griselda Bonilla , Xiao Hu Liu , Son Van Nguyen , Thomas M. Shaw , Hosadurga K. Shobha , Daewon Yang
发明人： Michael P. Belyansky , Griselda Bonilla , Xiao Hu Liu , Son Van Nguyen , Thomas M. Shaw , Hosadurga K. Shobha , Daewon Yang
IPC分类号： H01L23/58 , H01L21/318
CPC分类号： H01L21/02123 , H01L21/02126 , H01L21/02167 , H01L21/0217 , H01L21/02274 , H01L21/02348 , H01L21/318 , H01L21/3185 , H01L21/76826 , H01L21/76828 , H01L21/76834
摘要： A dielectric cap and related methods are disclosed. In one embodiment, the dielectric cap includes a dielectric material having an optical band gap (e.g. greater than about 3.0 electron-Volts) to substantially block ultraviolet radiation during a curing treatment, and including nitrogen with electron donor, double bond electrons. The dielectric cap exhibits a high modulus and is stable under post ULK UV curing treatments for, for example: copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability,
摘要翻译：公开了介电盖和相关方法。在一个实施例中，电介质盖包括具有光学带隙（例如大于约3.0电子伏特）的电介质材料，以在固化处理期间基本上阻挡紫外线辐射，并且包括氮与电子给体，双键电子。电介质盖表现出高模量，并且在ULK UV固化处理后稳定，例如：铜低k后端（BEOL）纳米电子器件，导致更少的膜和器件开裂和改善的可靠性，

42. 发明授权

US06972209B2 Stacked via-stud with improved reliability in copper metallurgy 失效
标题翻译：堆叠通孔，提高了铜冶金的可靠性
公开(公告)号：US06972209B2
公开(公告)日：2005-12-06
申请号：US10306534
申请日：2002-11-27
申请人： Birendra N. Agarwala , Conrad A. Barile , Hormazdyar M. Dalal , Brett H. Engle , Michael Lane , Ernest Levine , Xiao Hu Liu , Vincent McGahay , John F. McGrath , Conal E. Murray , Jawahar P. Nayak , Du B. Nguyen , Hazara S. Rathore , Thomas M. Shaw
发明人： Birendra N. Agarwala , Conrad A. Barile , Hormazdyar M. Dalal , Brett H. Engle , Michael Lane , Ernest Levine , Xiao Hu Liu , Vincent McGahay , John F. McGrath , Conal E. Murray , Jawahar P. Nayak , Du B. Nguyen , Hazara S. Rathore , Thomas M. Shaw
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/00
CPC分类号： H01L23/53295 , H01L21/76807 , H01L21/76829 , H01L21/76838 , H01L23/5226 , H01L2924/0002 , Y10T428/24917 , H01L2924/00
摘要： A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.
摘要翻译：一种多级半导体集成电路（IC）结构，包括在半导体衬底上包括电介质材料层的第一互连电平，所述介电材料层包括用于钝化半导体器件的致密材料和其下的局部互连; 形成在致密电介质材料层之上的电介质材料的多个互连层，每层介电材料包括至少一层低k电介质材料; 以及在低k电介质材料层中的一组堆叠的通孔螺钉，每组所述一组堆叠通孔柱互连一个或多个图案化导电结构，包括形成在低k电介质材料中的悬臂的导电结构。多个互连级别中的每一个的电介质层包括软的低k电介质材料，其中悬臂和一组堆叠的通孔螺钉集成在软低k电介质材料内，以增加对热疲劳裂纹形成的抵抗力。在一个实施例中，低k电介质材料层中的每组叠置通孔螺柱设置有悬臂，使得悬臂通过将一个级上的悬臂连接到相邻的导体线的主体部分而交织互连级别，从而增加互连级别之间堆叠通孔的灵活性。

43. 发明申请

US20120294322A1 Dislocation Engineering Using a Scanned Laser 审中-公开
标题翻译：使用扫描激光的位错工程
公开(公告)号：US20120294322A1
公开(公告)日：2012-11-22
申请号：US13565018
申请日：2012-08-02
申请人： Chung Woh Lai , Xiao Hu Liu , Anita Madan , Klaus W. Schwarz , J. Campbell Scott
发明人： Chung Woh Lai , Xiao Hu Liu , Anita Madan , Klaus W. Schwarz , J. Campbell Scott
IPC分类号： H01S3/10
CPC分类号： H01L21/3221 , H01L21/268 , H01L21/2686 , H01L21/3226 , H01L29/1054 , H01L29/7842
摘要： A system for manipulating dislocations on semiconductor devices, includes a moveable laser configured to generate a laser beam locally on a surface portion of the semiconductor body having a plurality of dislocations, the moveable laser being characterized as having a scan speed, the moveable laser manipulates the plurality of dislocations on the surface portion of the semiconductor body by adjusting the temperature and the scan speed of the laser beam.
摘要翻译：一种用于操纵半导体器件上的位错的系统，包括可移动激光器，其被配置为在具有多个位错的半导体主体的表面部分局部地产生激光束，所述可移动激光器的特征在于具有扫描速度，所述可移动激光器通过调整激光束的温度和扫描速度，半导体本体的表面部分上的多个位错。

44. 发明授权

US08278155B2 Reprogrammable fuse structure and method 有权
标题翻译：可编程熔丝结构及方法
公开(公告)号：US08278155B2
公开(公告)日：2012-10-02
申请号：US13100456
申请日：2011-05-04
申请人： Geoffrey W. Burr , Chandrasekharan Kothandaraman , Chung Hon Lam , Xiao Hu Liu , Stephen M. Rossnagel , Christy S. Tyberg , Robert L. Wisnieff
发明人： Geoffrey W. Burr , Chandrasekharan Kothandaraman , Chung Hon Lam , Xiao Hu Liu , Stephen M. Rossnagel , Christy S. Tyberg , Robert L. Wisnieff
IPC分类号： H01L21/82 , H01L21/326 , H01L21/479
CPC分类号： H01L23/5256 , H01L23/5252 , H01L45/06 , H01L45/1206 , H01L45/1226 , H01L45/1286 , H01L45/1293 , H01L45/144 , H01L45/148 , H01L45/1683 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.
摘要翻译：集成电路中的可逆熔丝结构通过实现具有短路相变材料的熔断电池获得，所述相变材料与能够使电流通过相变材料线（熔丝电池）的通孔和线结构相接触。电流通过熔丝电池，以便通过将结晶状态的相变材料加热至熔点，从而将材料从较小电阻的材料转变为更电阻的材料，然后快速将材料淬火成非晶状态。可逆编程通过使较低电流通过熔丝电池来实现，以将高电阻率无定形材料转换成较低电阻率的晶体材料。集成适当的感测电路以读取存储在熔丝中的信息，其中所述感测电路用于启用或禁用电路。

45. 发明授权

US08159854B2 Piezo-effect transistor device and applications 有权
标题翻译：压电效应晶体管器件及应用
公开(公告)号：US08159854B2
公开(公告)日：2012-04-17
申请号：US12495027
申请日：2009-06-30
申请人： Bruce G. Elmegreen , Lia Krusin-Elbaum , Glenn J. Martyna , Xiao Hu Liu , Dennis M. Newns
发明人： Bruce G. Elmegreen , Lia Krusin-Elbaum , Glenn J. Martyna , Xiao Hu Liu , Dennis M. Newns
IPC分类号： G11C5/06
CPC分类号： H03K19/02 , G11C11/412 , G11C13/0002 , H01L49/00 , Y10T29/42
摘要： A piezo-effect transistor (PET) device includes a piezoelectric (PE) material disposed between first and second electrodes; and a piezoresistive (PR) material disposed between the second electrode and a third electrode, wherein the first electrode comprises a gate terminal, the second electrode comprises a common terminal, and the third electrode comprises an output terminal such that an electrical resistance of the PR material is dependent upon an applied voltage across the PE material by way of an applied pressure to the PR material by the PE material.
摘要翻译：压电效应晶体管（PET）器件包括设置在第一和第二电极之间的压电（PE）材料; 以及设置在第二电极和第三电极之间的压阻（PR）材料，其中第一电极包括栅极端子，第二电极包括公共端子，并且第三电极包括输出端子，使得PR的电阻材料取决于PE材料上施加的电压，通过PE材料对PR材料的施加压力。

46. 发明授权

US08138066B2 Dislocation engineering using a scanned laser 有权
标题翻译：使用扫描激光的位错工程
公开(公告)号：US08138066B2
公开(公告)日：2012-03-20
申请号：US12242990
申请日：2008-10-01
申请人： Chung Woh Lai , Xiao Hu Liu , Anita Madan , Klaus W. Schwarz , J. Campbell Scott
发明人： Chung Woh Lai , Xiao Hu Liu , Anita Madan , Klaus W. Schwarz , J. Campbell Scott
IPC分类号： H01L21/322
CPC分类号： H01L21/3221 , H01L21/268 , H01L21/2686 , H01L21/3226 , H01L29/1054 , H01L29/7842
摘要： A method for generating patterned strained regions in a semiconductor device is provided. The method includes directing a light-emitting beam locally onto a surface portion of a semiconductor body; and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam, the light-emitting beam being characterized as having a scan speed, so as to produce the patterned strained regions.
摘要翻译：提供了一种在半导体器件中产生图案化应变区域的方法。该方法包括将发光束局部引导到半导体本体的表面部分上; 以及利用所述发光束操作位于所述半导体主体的表面部分附近的多个位错，所述发光束的特征在于具有扫描速度，以便产生所述图案化的应变区域。

47. 发明申请

US20100073997A1 PIEZO-DRIVEN NON-VOLATILE MEMORY CELL WITH HYSTERETIC RESISTANCE 有权
标题翻译： PIEZO-DRIVEN非易失性记忆体具有耐久性
公开(公告)号：US20100073997A1
公开(公告)日：2010-03-25
申请号：US12234100
申请日：2008-09-19
申请人： Bruce G. Elmegreen , Lia Krusin-Elbaum , Xiao Hu Liu , Glenn J. Martyna , Martin Muser , Dennis M. Newns
发明人： Bruce G. Elmegreen , Lia Krusin-Elbaum , Xiao Hu Liu , Glenn J. Martyna , Martin Muser , Dennis M. Newns
IPC分类号： G11C11/00 , H04R17/00 , G11C7/00
CPC分类号： G11C23/00 , G11C13/0002 , G11C13/0004 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1206 , H01L45/1233 , H01L45/142 , H01L45/148 , Y10T29/42
摘要： A piezoelectrically programmed, non-volatile memory cell structure includes a programmable piezo-resistive hysteretic material (PRHM) that is capable of being interconverted between a low resistance state and high resistance state through applied pressure cycling thereto; a piezoelectric material mechanically coupled to the PHRM such that an applied voltage across the piezoelectric material results in one of a tensile or compressive stress applied to the PRHM, depending upon the polarity of the applied voltage; and one or more electrodes in electrical communication with the PRHM, wherein the one or more electrodes are configured to provide a write programming current path through the piezoelectric material and a read current path through the PRHM.
摘要翻译：压电编程的非易失性存储单元结构包括可编程压阻滞回材料（PRHM），其能够通过施加的压力循环而在低电阻状态和高电阻状态之间相互转换; 机械地耦合到PHRM的压电材料，使得跨压电材料施加的电压导致施加到PRHM的拉伸或压缩应力中的一个，这取决于所施加的电压的极性; 以及与PRHM电连通的一个或多个电极，其中所述一个或多个电极被配置为提供通过所述压电材料的写入编程电流路径和通过所述PRHM的读取电流路径。

48. 发明申请

US20100013043A1 CRACKSTOP STRUCTURES AND METHODS OF MAKING SAME 有权
标题翻译： CRACKSTOP结构及其制造方法
公开(公告)号：US20100013043A1
公开(公告)日：2010-01-21
申请号：US12174994
申请日：2008-07-17
申请人： Xiao Hu Liu , Chih-Chao Yang , Haining Sam Yang
发明人： Xiao Hu Liu , Chih-Chao Yang , Haining Sam Yang
IPC分类号： H01L29/00 , H01L21/00
CPC分类号： H01L23/585 , H01L23/3171 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a continuous first stress ring proximate to a perimeter of the integrated circuit chip, respective edges of the first stress ring parallel to respective edges of the integrated circuit chip; a continuous second stress ring between the first stress ring and the perimeter of the integrated circuit chip, respective edges the second stress ring parallel to respective edges of the integrated circuit chip, the first and second stress rings having opposite internal stresses; a continuous gap between the first stress ring and the second stress ring; and a set of wiring levels from a first wiring level to a last wiring level on the substrate.
摘要翻译：集成电路芯片和制造集成电路芯片的方法。集成电路芯片包括：接近集成电路芯片的周边的连续的第一应力环，第一应力环的相应边缘平行于集成电路芯片的相应边缘; 所述第一应力环与所述集成电路芯片的周边之间的连续的第二应力环，所述第二应力环平行于所述集成电路芯片的相应边缘的相应边缘，所述第一和第二应力环具有相反的内应力; 第一应力环和第二应力环之间的连续间隙; 以及从基板上的第一布线电平到最后布线电平的一组布线电平。

49. 发明申请

US20080217663A1 Enhanced Transistor Performance by Non-Conformal Stressed Layers 有权
标题翻译：通过非保形强制层增强晶体管性能
公开(公告)号：US20080217663A1
公开(公告)日：2008-09-11
申请号：US11682554
申请日：2007-03-06
申请人： Bruce B. Doris , Xiao Hu Liu
发明人： Bruce B. Doris , Xiao Hu Liu
IPC分类号： H01L27/098 , H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： NFET and PFET devices with separately strained channel regions, and methods of their fabrication is disclosed. A stressing layer overlays the device in a manner that the stressing layer is non-conformal with respect the gate. The non-conformality of the stressing layer increases the amount of stress that is imparted onto the channel of the device, in comparison to stressing layers which are conformal. The method for overlaying in a non-conformal manner includes non-conformal deposition techniques, as well as, conformal depositions where subsequently the layer is turned into a non-conformal one by etching.
摘要翻译：公开了具有单独应变通道区域的NFET和PFET器件及其制造方法。应力层以使得应力层相对于浇口不共面的方式覆盖该装置。与应力层相比，应力层的非共形性增加了施加到器件的通道上的应力的量。以非共形方式覆盖的方法包括非共形沉积技术以及保形沉积，其中随后通过蚀刻将该层转变为非共形沉积技术。

50. 发明授权

US07394089B2 Heat-shielded low power PCM-based reprogrammable EFUSE device 有权
标题翻译：隔热低功耗基于PCM的可编程EFUSE设备
公开(公告)号：US07394089B2
公开(公告)日：2008-07-01
申请号：US11467294
申请日：2006-08-25
申请人： James P. Doyle , Bruce G. Elmegreen , Lia Krusin-Elbaum , Chung Hon Lam , Xiao Hu Liu , Dennis M. Newns , Christy S. Tyberg
发明人： James P. Doyle , Bruce G. Elmegreen , Lia Krusin-Elbaum , Chung Hon Lam , Xiao Hu Liu , Dennis M. Newns , Christy S. Tyberg
IPC分类号： H01L47/00
CPC分类号： H01L45/1233 , G11C13/0004 , H01L45/06 , H01L45/1206 , H01L45/1286 , H01L45/1293 , H01L45/144 , H01L45/148 , H01L45/1666
摘要： An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.
摘要翻译：用于集成电路器件的电可重新编程保险丝（eFUSE）器件包括细长的加热器元件，围绕细长加热器元件的外表面的电绝缘衬垫，其对应于其纵向轴线，留下细长加热器的相对端元件与第一和第二加热器电极电接触。相变材料（PCM）围绕电绝缘衬垫的外表面的一部分，热和电绝缘层围绕PCM的外表面，其中第一和第二熔丝电极与PCM的相对端电接触。 PCM被封装在电绝缘衬垫，热和电绝缘层以及第一和第二熔丝电极中。

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