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    • 41. 发明申请
    • LOAD MULTIPLE AND STORE MULTIPLE INSTRUCTIONS IN A MICROPROCESSOR THAT EMULATES BANKED REGISTERS
    • 加载多个寄存器的微处理器中的多个和存储多个指令
    • US20120260042A1
    • 2012-10-11
    • US13413314
    • 2012-03-06
    • G. Glenn HenryTerry ParksRodney E. Hooker
    • G. Glenn HenryTerry ParksRodney E. Hooker
    • G06F15/76G06F9/06G06F12/08
    • G06F9/22G06F9/3017G06F9/30174G06F9/30189G06F12/0875
    • A microprocessor supports an instruction set architecture that specifies: processor modes, architectural registers associated with each mode, and a load multiple instruction that instructs the microprocessor to load data from memory into specified ones of the registers. Direct storage holds data associated with a first portion of the registers and is coupled to an execution unit to provide the data thereto. Indirect storage holds data associated with a second portion of the registers and cannot directly provide the data to the execution unit. Which architectural registers are in the first and second portions varies dynamically based upon the current processor mode. If a specified register is currently in the first portion, the microprocessor loads data from memory into the direct storage, whereas if in the second portion, the microprocessor loads data from memory into the direct storage and then stores the data from the direct storage to the indirect storage.
    • 微处理器支持指令集架构,其指定:处理器模式,与每种模式相关联的架构寄存器,以及指令微处理器将数据从存储器加载到指定寄存器中的加载多指令。 直接存储保持与寄存器的第一部分相关联的数据,并且耦合到执行单元以向其提供数据。 间接存储保存与寄存器的第二部分相关联的数据,并且不能将数据直接提供给执行单元。 第一和第二部分中的哪些架构寄存器基于当前的处理器模式动态变化。 如果指定的寄存器当前位于第一部分,则微处理器将数据从存储器加载到直接存储器中,而如果在第二部分中,微处理器将数据从存储器加载到直接存储器中,然后将数据从直接存储器存储到 间接存储。
    • 42. 发明授权
    • Apparatus and method for extending a microprocessor instruction set
    • 用于扩展微处理器指令集的装置和方法
    • US07543134B2
    • 2009-06-02
    • US11001212
    • 2004-12-01
    • G. Glenn HenryRodney E. HookerTerry Parks
    • G. Glenn HenryRodney E. HookerTerry Parks
    • G06F9/30G06F9/00
    • G06F9/30174G06F9/30185
    • An apparatus and method for extending a microprocessor instruction set is provided. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has an extended prefix and an extended instruction tag. The extended prefix directs that an architectural extension be employed in the execution of an operation prescribed by the extended instruction. The extended instruction tag indicates the extended instruction prefix, where the extended instruction tag is an otherwise architecturally specified opcode within the microprocessor instruction set. The extended execution logic is coupled to the translation logic, and receives the corresponding micro instructions, and employs the architectural extension in the execution of the operation.
    • 提供了一种用于扩展微处理器指令集的装置和方法。 该装置包括翻译逻辑和扩展执行逻辑。 翻译逻辑将扩展指令转换为相应的微指令。 扩展指令具有扩展前缀和扩展指令标记。 扩展前缀指示在执行扩展指令规定的操作时采用架构扩展。 扩展指令标签指示扩展指令前缀,其中扩展指令标签是微处理器指令集中的另外结构上指定的操作码。 扩展执行逻辑被耦合到转换逻辑,并且接收相应的微指令,并且在执行操作时采用架构扩展。
    • 44. 发明授权
    • Mechanism for extending the number of registers in a microprocessor
    • 扩展微处理器寄存器数量的机制
    • US07373483B2
    • 2008-05-13
    • US10144590
    • 2002-05-09
    • G. Glenn HenryRodney E. HookerTerry Parks
    • G. Glenn HenryRodney E. HookerTerry Parks
    • G06F9/30G06F9/00
    • G06F9/30145G06F9/30098G06F9/30138G06F9/30174G06F9/30185G06F9/30189
    • An apparatus and method are provided, for accessing extended registers within a microprocessor. The apparatus includes translation logic and extended register logic. The translation logic translates an extended instruction into corresponding micro instructions for execution by the microprocessor. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies register address extensions, the register address extensions indicating the extended registers, where the extended registers cannot be specified by an existing instruction set, and where the existing instruction set includes the x86 instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set, and where the extended prefix tag includes opcode F1 (ICE BKPT) in the x86 instruction set. The extended register logic is coupled to the translation logic. The extended register logic receives the corresponding micro instructions, and for accesses the extended registers.
    • 提供了一种用于访问微处理器内的扩展寄存器的装置和方法。 该装置包括翻译逻辑和扩展寄存器逻辑。 翻译逻辑将扩展指令转换成相应的微指令以由微处理器执行。 扩展指令具有扩展前缀和扩展前缀标记。 扩展前缀指定寄存器地址扩展,寄存器地址扩展表示扩展寄存器,扩展寄存器不能由现有指令集指定,而现有指令集包含x86指令集。 扩展前缀标记指示扩展前缀,其中扩展前缀标记是现有指令集中的结构上指定的操作码,扩展前缀标记在x86指令集中包含操作码F1(ICE BKPT)。 扩展寄存器逻辑耦合到转换逻辑。 扩展寄存器逻辑接收相应的微指令,并用于访问扩展寄存器。
    • 45. 发明授权
    • Non-temporal memory reference control mechanism
    • 非时间内存参考控制机制
    • US07328328B2
    • 2008-02-05
    • US10227583
    • 2002-08-22
    • G. Glenn HenryRodney E. HookerTerry Parks
    • G. Glenn HenryRodney E. HookerTerry Parks
    • G06F9/318G06F9/34
    • G06F9/30189G06F9/30185G06F9/3824G06F12/0862
    • An apparatus and method are provided for extending a microprocessor instruction set to specify non-temporal memory references at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into a micro instruction sequence. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies a non-temporal access for a memory reference prescribed by the extended instruction, where the non-temporal access cannot be specified by an existing instruction from an existing instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the micro instruction sequence, and executes the non-temporal access to perform the memory reference.
    • 提供了一种用于扩展微处理器指令集以在指令级别指定非时间存储器引用的装置和方法。 该装置包括翻译逻辑和扩展执行逻辑。 翻译逻辑将扩展指令转换为微指令序列。 扩展指令具有扩展前缀和扩展前缀标记。 扩展前缀指定由扩展指令规定的存储器引用的非时间访问,其中非时间访问不能由来自现有指令集的现有指令指定。 扩展前缀标记指示扩展前缀,其中扩展前缀标记是现有指令集中另外以结构体系指定的操作码。 扩展执行逻辑耦合到转换逻辑。 扩展执行逻辑接收微指令序列,并执行非时间访问以执行存储器引用。
    • 46. 发明授权
    • Apparatus and method for selective control of condition code write back
    • 用于选择性地控制条件代码回写的装置和方法
    • US07185180B2
    • 2007-02-27
    • US10144593
    • 2002-05-09
    • G. Glenn HenryRodney E. HookerTerry Parks
    • G. Glenn HenryRodney E. HookerTerry Parks
    • G06F9/30
    • G06F9/30094G06F9/30185G06F9/30189G06F9/3842
    • A microprocessor apparatus and method are provided, for selectively controlling write back of condition codes. The microprocessor apparatus has translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction includes an extended prefix and an extended prefix tag. The extended prefix disables write back of the condition codes, where the condition codes correspond to a result of a prescribed operation. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within an instruction set for a microprocessor. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and generates the result, and disables write back of the condition codes.
    • 提供了一种微处理器装置和方法,用于选择性地控制条件代码的回写。 微处理器装置具有翻译逻辑和扩展执行逻辑。 翻译逻辑将扩展指令转换为相应的微指令。 扩展指令包括扩展前缀和扩展前缀标记。 扩展前缀禁止写条件代码,其中条件代码对应于规定操作的结果。 扩展前缀标记指示扩展前缀,其中扩展前缀标记是用于微处理器的指令集内的另外结构上指定的操作码。 扩展执行逻辑耦合到转换逻辑。 扩展执行逻辑接收相应的微指令,并产生结果,并禁止对条件代码的回写。
    • 49. 发明申请
    • CONTROL REGISTER MAPPING IN HETEROGENEOUS INSTRUCTION SET ARCHITECTURE PROCESSOR
    • 异构指令集建筑处理器中的控制寄存器映射
    • US20130067199A1
    • 2013-03-14
    • US13413346
    • 2012-03-06
    • G. Glenn HenryTerry ParksRodney E. Hooker
    • G. Glenn HenryTerry ParksRodney E. Hooker
    • G06F9/318
    • G06F9/30174G06F9/30076G06F9/30101G06F9/30112G06F9/3017G06F9/30189G06F9/30196
    • A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR.
    • 能够运行x86指令集架构(ISA)机器语言程序和高级RISC机(ARM)ISA机器语言程序的微处理器。 微处理器包括指示微处理器当前是否正在获取x86 ISA或ARM ISA机器语言程序的指令的模式指示器。 微处理器还包括多个模型专用寄存器(MSR),其控制微处理器操作的方面。 当模式指示符指示微处理器当前正在获取x86 ISA机器语言程序指令时,可通过指定MSR的地址的x86 ISA RDMSR / WRMSR指令访问多个MSR中的每一个。 当模式指示符指示微处理器当前正在获取ARM ISA机器语言程序指令时,可通过指定MSR的地址的ARM ISA MRRC / MCRR指令访问多个MSR中的每一个。