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41. 发明申请

US20050221200A1 Photomask features with chromeless nonprinting phase shifting window 审中-公开
标题翻译：具有无色非印刷相移窗的光掩模特征
公开(公告)号：US20050221200A1
公开(公告)日：2005-10-06
申请号：US10815312
申请日：2004-04-01
申请人： Yung-Tin Chen
发明人： Yung-Tin Chen
IPC分类号： G03F1/00 , G03F9/00 , G06F17/50
CPC分类号： G03F1/34 , G03F1/36
摘要： Aspects of the present invention provide for a novel photomask for patterning features for an integrated circuit, the photomask including a first area transmitting light in a first phase surrounded by second area, the second area transmitting light in a second phase, the second phase opposite the first phase. No blocking material separates the first area from the second area. After development of photoresist, the transition between the first and second area causes formation of a residual photoresist feature on the photoresist surface due to phase canceling of light. If the first area is small enough, it is nonprinting, ie., the opposite sides of the residual photoresist feature formed at its perimeter merge, forming a contiguous photoresist feature, and thus a corresponding patterned feature after etch.
摘要翻译：本发明的方面提供了一种用于集成电路的图形化特征的新型光掩模，所述光掩模包括第一区域，所述第一区域透射由第二区域包围的第一相中的光，所述第二区域在第二相中透射光，所述第二相位与所述第二相位相反，第一阶段没有阻挡材料将第一区域与第二区域分开。在光致抗蚀剂显影之后，第一和第二区域之间的转变导致光致抗蚀剂表面上残留光致抗蚀剂特征的形成，这是由于相消光。如果第一区域足够小，则其是非印刷的，即，在其周边处形成的残余光致抗蚀剂特征的相对侧合并，形成连续的光致抗蚀剂特征，并因此形成蚀刻后的相应的图案化特征。

42. 发明申请

US20050133827A1 Large-scale trimming for ultra-narrow gates 有权
标题翻译：超窄门的大规模修剪
公开(公告)号：US20050133827A1
公开(公告)日：2005-06-23
申请号：US10738239
申请日：2003-12-17
申请人： Ming-Jie Huang , Shu-Chih Yang , Huan-Just Lin , Yung-Tin Chen , Hun-Jan Tao
发明人： Ming-Jie Huang , Shu-Chih Yang , Huan-Just Lin , Yung-Tin Chen , Hun-Jan Tao
IPC分类号： H01L21/28 , H01L21/3213 , H01L29/745
CPC分类号： H01L21/32139 , H01L21/28123
摘要： Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the width of the hard mask layer, where the soft mask layer has been removed. At least a gate electrode layer below the hard mask layer on the semiconductor wafer is etched, resulting in the gate electrode layer having a width substantially identical to the width of the hard mask layer as trimmed. The gate electrode layer as etched forms the ultra-narrow gate electrode on the semiconductor wafer, where the hard mask layer has been removed.
摘要翻译：公开了用于形成用于半导体器件的超窄栅极的大规模修整。蚀刻在半导体晶片上的图案化软掩模层下方的半导体晶片上的硬掩模层，以使硬掩模层的宽度变窄。修剪硬掩模层以进一步缩小已经去除软掩模层的硬掩模层的宽度。蚀刻半导体晶片上的硬掩模层下方的至少栅极电极层，导致栅极电极层的宽度与被修整的硬掩模层的宽度基本相同。蚀刻的栅极电极层形成半导体晶片上的超窄栅电极，其中硬掩模层被去除。

43. 发明申请

US20050123837A1 Photomask features with interior nonprinting window using alternating phase shifting 有权
标题翻译：光掩模功能与内部非打印窗口使用交替相移
公开(公告)号：US20050123837A1
公开(公告)日：2005-06-09
申请号：US10728436
申请日：2003-12-05
申请人： Yung-Tin Chen
发明人： Yung-Tin Chen
IPC分类号： G03C5/00 , G03F1/00 , G03F9/00
CPC分类号： G03F1/30
摘要： Aspects of the present invention provide for a novel photomask for patterning features for an integrated circuit, the photomask including masked features having interior nonprinting windows. In some embodiments, the interior nonprinting window is an alternating phase shifter, while the area surrounding the masked features transmits light unshifted. In other embodiments, the interior nonprinting window transmits light unshifted, while the area surrounding the masked features is an alternating phase shifter. Thus any arrangement of features can be patterned with no phase conflict.
摘要翻译：本发明的方面提供了一种用于集成电路的图形化特征的新型光掩模，该光掩模包括具有内部非印刷窗口的掩蔽特征。在一些实施例中，内部非打印窗口是交替移相器，而围绕被掩蔽的特征的区域透射未被移动的光。在其他实施例中，内部非打印窗口透射未被移动的光，而围绕屏蔽特征的区域是交替移相器。因此，可以对任何特征的布置进行图案化而没有相位冲突。

44. 发明授权

US11462567B2 Three-dimensional ferroelectric random-access memory (FeRAM) 有权
公开(公告)号：US11462567B2
公开(公告)日：2022-10-04
申请号：US17039746
申请日：2020-09-30
申请人： Yung-Tin Chen
发明人： Yung-Tin Chen
IPC分类号： H01L27/11 , H01L27/11597 , H01L27/11587 , G11C11/22
摘要： A 3-dimensional vertical memory string array includes high-speed ferroelectric field-effect transistor (FET) cells that are low-cost, low-power, or high-density and suitable for SCM applications. The memory circuits of the present invention provide random-access capabilities. The memory string may be formed above a planar surface of substrate and include a vertical gate electrode extending lengthwise along a vertical direction relative to the planar surface and may include (i) a ferroelectric layer over the gate electrode, (ii) a gate oxide layer; (iii) a channel layer provided over the gate oxide layer; and (iv) conductive semiconductor regions embedded in and isolated from each other by an oxide layer, wherein the gate electrode, the ferroelectric layer, the gate oxide layer, the channel layer and each adjacent pair of semiconductor regions from a storage transistor of the memory string, and wherein the adjacent pair of semiconductor regions serve as source and drain regions of the storage transistor.

45. 发明授权

US08389971B2 Memory cells having storage elements that share material layers with steering elements and methods of forming the same 有权
标题翻译：具有与转向元件共享材料层的存储元件的存储单元及其形成方法
公开(公告)号：US08389971B2
公开(公告)日：2013-03-05
申请号：US12905047
申请日：2010-10-14
申请人： Yung-Tin Chen , Chuanbin Pan , Andrei Mihnea , Steven Maxwell , Kun Hou
发明人： Yung-Tin Chen , Chuanbin Pan , Andrei Mihnea , Steven Maxwell , Kun Hou
IPC分类号： H01L47/00
CPC分类号： H01L45/146 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1616 , Y10S438/957
摘要： In some embodiments, a memory cell is provided that includes a storage element formed from an MIM stack including (1) a first conductive layer; (2) an RRS layer formed above the first conductive layer; and (3) a second conductive layer formed above the RRS layer, at least one of the first and second conductive layers comprising a first semiconductor material layer. The memory cell includes a steering element coupled to the storage element, the steering element formed from the first semiconductor material layer of the MIM stack and one or more additional material layers. Numerous other aspects are provided.
摘要翻译：在一些实施例中，提供了一种存储单元，其包括由MIM堆叠形成的存储元件，所述存储元件包括：（1）第一导电层; （2）形成在第一导电层上方的RRS层; 和（3）形成在RRS层之上的第二导电层，第一和第二导电层中的至少一个包括第一半导体材料层。存储单元包括耦合到存储元件的操纵元件，由MIM堆叠的第一半导体材料层形成的操纵元件和一个或多个附加材料层。提供了许多其他方面。

46. 发明授权

US08372740B2 Methods for increased array feature density 有权
标题翻译：增加数组特征密度的方法
公开(公告)号：US08372740B2
公开(公告)日：2013-02-12
申请号：US13366916
申请日：2012-02-06
申请人： Huiwen Xu , Yung-Tin Chen , Steven J. Radigan
发明人： Huiwen Xu , Yung-Tin Chen , Steven J. Radigan
IPC分类号： H01L21/44
CPC分类号： H01L21/3088 , H01L21/0337 , H01L21/0338 , H01L27/101 , H01L27/1021
摘要： The embodiments generally relate to methods of making semiconductor devices, and more particularly, to methods for making semiconductor pillar structures and increasing array feature pattern density using selective or directional gap fill. The technique has application to a variety of materials and can be applied to making monolithic two or three-dimensional memory arrays.
摘要翻译：实施例通常涉及制造半导体器件的方法，更具体地，涉及制造半导体柱结构的方法以及使用选择性或方向性间隙填充来增加阵列特征图案密度。该技术可应用于各种材料，可应用于制作单片二维或三维存储阵列。

47. 发明申请

US20120127779A1 Re-writable Resistance-Switching Memory With Balanced Series Stack 有权
标题翻译：具有平衡串联堆叠的可重写电阻切换存储器
公开(公告)号：US20120127779A1
公开(公告)日：2012-05-24
申请号：US13363252
申请日：2012-01-31
申请人： Roy E. Scheuerlein , Henry Chien , Zhida Lan , Yung-Tin Chen
发明人： Roy E. Scheuerlein , Henry Chien , Zhida Lan , Yung-Tin Chen
IPC分类号： G11C11/00
CPC分类号： H01L45/146 , G11C5/02 , G11C8/08 , G11C8/12 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C2013/0073 , G11C2213/33 , G11C2213/71 , H01L27/2409 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/145
摘要： A re-writable resistance-switching memory cell includes first and second capacitors in series. The first and second capacitors may have balanced electrical characteristics to allow nearly concurrent, same-direction switching. The first capacitor has a first bipolar resistance switching layer between first and second conductive layers, and the second capacitor has a second bipolar resistance switching layer between third and fourth conductive layers. The first and third conductive layers are made of a common material, and the second and fourth conductive layers are made of a common material. In one approach, the first and second bipolar resistance switching layers are made of a common material and have common thickness. In another approach, the first and second bipolar resistance switching layers are made of materials having different dielectric constants, but their thickness differs in proportion to the difference in the dielectric constants, to provide a common capacitance per unit area.
摘要翻译：可重写电阻切换存储单元包括串联的第一和第二电容器。第一和第二电容器可以具有平衡的电气特性，以允许几乎同时进行相同方向的切换。第一电容器具有在第一和第二导电层之间的第一双极性电阻开关层，并且第二电容器在第三和第四导电层之间具有第二双极性电阻开关层。第一和第三导电层由普通材料制成，第二和第四导电层由普通材料制成。在一种方法中，第一和第二双极性电阻切换层由普通材料制成并且具有共同的厚度。在另一种方法中，第一和第二双极性电阻开关层由具有不同介电常数的材料制成，但它们的厚度与介电常数的差异成比例，以提供每单位面积的公共电容。

48. 发明申请

US20120091427A1 MULTI-LEVEL MEMORY ARRAYS WITH MEMORY CELLS THAT EMPLOY BIPOLAR STORAGE ELEMENTS AND METHODS OF FORMING THE SAME 有权
标题翻译：具有使用双极存储元件的存储器单元的多级存储器阵列及其形成方法
公开(公告)号：US20120091427A1
公开(公告)日：2012-04-19
申请号：US12904802
申请日：2010-10-14
申请人： Yung-Tin Chen , Andrei Mihnea , Roy E. Scheuerlein , Luca Fasoli
发明人： Yung-Tin Chen , Andrei Mihnea , Roy E. Scheuerlein , Luca Fasoli
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L27/2481 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.
摘要翻译：在一些实施例中，提供了一种存储器阵列，其包括（1）具有（a）第一导电线的第一存储器单元; （b）形成在第一导线之上的第一双极存储元件; 和（c）形成在所述第一双极存储元件上方的第二导线; 以及（2）形成在所述第一存储单元上方的第二存储单元，并且具有（a）形成在所述第二导线上方的第二双极存储元件; 和（b）形成在第二双极存储元件上方的第三导线。第一和第二存储单元共享第二导线; 第一双极存储元件在第一存储单元内具有第一存储元件极性取向; 所述第二双极存储元件在所述第二存储单元内具有第二存储元件极性取向; 并且第二存储元件极性取向与第一存储元件极性取向相反。提供了许多其他方面。

49. 发明授权

US08076056B2 Method of making sub-resolution pillar structures using undercutting technique 有权
标题翻译：使用底切技术制作分辨率柱状结构的方法
公开(公告)号：US08076056B2
公开(公告)日：2011-12-13
申请号：US12285466
申请日：2008-10-06
申请人： Chun-Ming Wang , Steven Maxwell , Paul Wai Kie Poon , Yung-Tin Chen
发明人： Chun-Ming Wang , Steven Maxwell , Paul Wai Kie Poon , Yung-Tin Chen
IPC分类号： G03F7/26
CPC分类号： H01L21/0334 , H01L21/0338
摘要： A method of making a device includes forming an underlying mask layer over an underlying layer, forming a first mask layer over the underlying mask layer, patterning the first mask layer to form first mask features, undercutting the underlying mask layer to form underlying mask features using the first mask features as a mask, removing the first mask features, and patterning the underlying layer using at least the underlying mask features as a mask.
摘要翻译：一种制造器件的方法包括在下面的层上形成下面的掩模层，在下面的掩模层之上形成第一掩模层，对第一掩模层进行图案化以形成第一掩模特征，利用下面的掩模层来切割下面的掩模特征，使用第一掩模作为掩模，去除第一掩模特征，并使用至少底层掩模特征作为掩模来图案化底层。

50. 发明授权

US07982273B2 Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure 有权
标题翻译：掩盖重复的覆盖和对准标记，以允许在垂直结构中重复使用光掩模
公开(公告)号：US07982273B2
公开(公告)日：2011-07-19
申请号：US12470886
申请日：2009-05-22
申请人： Yung-Tin Chen , Christopher J. Petti , Steven J. Radigan , Tanmay Kumar
发明人： Yung-Tin Chen , Christopher J. Petti , Steven J. Radigan , Tanmay Kumar
IPC分类号： H01L29/76
CPC分类号： H01L27/0688 , G03F7/70633 , G03F9/7084 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446
摘要： A monolithic three dimensional semiconductor device structure includes a first layer including a first occurrence of a first reference mark at a first location, and a second layer including a second occurrence of the first reference mark at a second location, wherein the second location is substantially directly above the first location. The device structure also includes an intermediate layer between the first layer and the second layer, the intermediate layer including a blocking structure, wherein the blocking structure is vertically interposed between the first occurrence of the first reference mark and the second occurrence of the first reference mark. Other aspects are also described.
摘要翻译：单片三维半导体器件结构包括第一层，其包括在第一位置处的第一参考标记的第一次出现，以及包括在第二位置处的第二参考标记的第二次出现的第二层，其中第二位置基本上直接在第一个位置以上。所述器件结构还包括在所述第一层和所述第二层之间的中间层，所述中间层包括阻挡结构，其中所述阻挡结构垂直插入所述第一参考标记的第一次出现和所述第一参考标记的第二次出现之间。还描述了其他方面。

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