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    • 42. 发明授权
    • Semiconductor configuration having trenches for isolating doped regions
    • 具有用于隔离掺杂区域的沟槽的半导体构造
    • US06445048B1
    • 2002-09-03
    • US09657074
    • 2000-09-07
    • Frank Pfirsch
    • Frank Pfirsch
    • H01L29772
    • H01L29/66348H01L21/763H01L29/0619H01L29/0638H01L29/0653H01L29/404H01L29/407H01L29/7397
    • A semiconductor configuration includes a substrate having a first conduction type. A transistor configuration is disposed at the substrate and is formed from at least one field-effect transistor having at least two doped regions embedded in the substrate and at least one gate electrode. The regions have a second conduction type, are disposed between the transistor configuration and the substrate edge, and extend from the substrate surface into the substrate and surround the transistor configuration. At least two adjacent insulating trench regions are disposed between the regions and extend from the substrate surface into the substrate for isolating the doped regions from one another. The trenches may have a smaller depth than the doped regions. A method for fabricating a semiconductor configuration includes providing a substrate having a first conduction type and producing regions in the substrate by introducing a dopant. The regions have a second conduction type. They extend from the surface of the substrate into the substrate and are isolated from one another in the substrate. A trench is produced at the boundary of each one of the regions facing a respective other one of the regions. Each trench has a depth greater than a depth of the respective at least two regions after introducing the dopant but less than a desired depth of the regions. The dopant is outdiffused to a desired depth greater than the depth of each respective trench. Each trench is filled by forming an insulating layer therein.
    • 半导体结构包括具有第一导电类型的衬底。 晶体管配置设置在衬底上并且由至少一个场效应晶体管形成,该场效应晶体管具有嵌入衬底中的至少两个掺杂区域和至少一个栅电极。 这些区域具有第二导电类型,设置在晶体管配置和衬底边缘之间,并且从衬底表面延伸到衬底中并且围绕晶体管配置。 至少两个相邻的绝缘沟槽区域设置在区域之间并且从衬底表面延伸到衬底中,用于将掺杂区域彼此隔离。 沟槽可以具有比掺杂区域更小的深度。 制造半导体结构的方法包括提供具有第一导电类型的衬底,并通过引入掺杂剂在衬底中产生区域。 这些区域具有第二导电类型。 它们从衬底的表面延伸到衬底中并且在衬底中彼此隔离。 在面对相应的另一个区域的每个区域的边界处产生沟槽。 每个沟槽在引入掺杂剂之后具有大于相应的至少两个区域的深度的深度,但是小于所述区域的期望深度。 掺杂剂超出比每个相应沟槽的深度大的期望深度。 通过在其中形成绝缘层来填充每个沟槽。
    • 44. 发明授权
    • Thyristor with integrated dU/dt protection
    • 具有集成dU / dt保护的晶闸管
    • US6066864A
    • 2000-05-23
    • US194178
    • 1998-11-20
    • Martin RuffHans-Joachim SchulzeFrank Pfirsch
    • Martin RuffHans-Joachim SchulzeFrank Pfirsch
    • H01L29/10H01L29/74
    • H01L29/7424H01L29/102H01L29/7428
    • Given too great a dU/dt load of a thyristor, this can trigger in uncontrolled fashion in the region of the cathode surface. Since the plasma only propagates poorly there and the current density consequently reaches critical values very quickly, there is the risk of destruction of the thyristor due to local overheating. The proposed thyristor has a centrally placed BOD structure and a plurality of auxiliary thyristors (1.-5. AG) annularly surrounding the BOD structure. The resistance of the cathode-side base (8) is locally increased under the emitter region (11) allocated to the innermost auxiliary thyristor (1. AG). Since the width (L) and the sheet resistivity of this annular zone (15) critically influences the dU/dt loadability of the first auxiliary thyristor (1. AG), a suitable dimensioning of these parameters assures that the central thyristor region comprises the smallest dU/dt sensitivity of the system and, accordingly, it also ignites first given upward transgression of a critical value of the voltage steepness.
    • PCT No.PCT / DE97 / 00927 Sec。 371日期:1998年11月20日 102(e)1998年11月20日日期PCT提交1997年5月7日PCT公布。 公开号WO97 / 44827 日期1997年11月27日由于晶闸管的dU / dt负载太大,这可能会在阴极表面的区域以不受控制的方式触发。 由于等离子体仅在那里传播不良,电流密度因此很快达到临界值,所以存在由于局部过热而导致晶闸管损坏的风险。 所提出的晶闸管具有中心放置的BOD结构和环绕着BOD结构的多个辅助晶闸管(1.-5·AG)。 在分配给最内侧辅助晶闸管(1.AG)的发射极区域(11)处,阴极侧基极(8)的电阻局部增加。 由于该环形区域(15)的宽度(L)和薄层电阻率严重影响第一辅助晶闸管(1.AG)的dU / dt负载能力,所以这些参数的合适尺寸确保了中央晶闸管区域包括最小 系统的dU / dt灵敏度,因此也会首先给出电压陡度的临界值的向上偏移。