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41. 发明申请

US20100052081A1 A SEALING STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：密封结构及其制造方法
公开(公告)号：US20100052081A1
公开(公告)日：2010-03-04
申请号：US12515590
申请日：2007-11-15
申请人： Johannes Donkers , Erwin Hijzen , Philippe Meunier-Beillard , Gerhard Koops
发明人： Johannes Donkers , Erwin Hijzen , Philippe Meunier-Beillard , Gerhard Koops
IPC分类号： H01L29/84 , H01L21/306
CPC分类号： B81C1/00293 , B81B2201/0271 , B81C2203/0145
摘要： A method of manufacturing a structure (1100), the method comprising forming a cap element (401) on a substrate (101), removing material (103) of the substrate (101) below the cap element (401) to thereby form a gap (802) between the cap element (401) and the substrate (101), and rearranging material of the cap element (401) and/or of the substrate (101) to thereby merge the cap element (401) and the substrate (101) to bridge the gap (802).
摘要翻译：一种制造结构（1100）的方法，所述方法包括在基板（101）上形成盖元件（401），在盖元件（401）下方去除基板（101）的材料（103），从而形成间隙（401）和基板（101）之间的盖（802）和盖元件（401）和/或基板（101）的重新排列材料，从而合并盖元件（401）和基板（101））弥合差距（802）。

42. 发明申请

US20080194069A1 Method of Manufacturing a Semiconductor Device and Semiconductor Device Obtained With Such a Method 有权
标题翻译：制造使用这种方法获得的半导体器件和半导体器件的方法
公开(公告)号：US20080194069A1
公开(公告)日：2008-08-14
申请号：US11574341
申请日：2005-08-10
申请人： Radu Surdeanu , Erwin Hijzen , Michael Antoine Zandt , Raymond Josephus Hueting
发明人： Radu Surdeanu , Erwin Hijzen , Michael Antoine Zandt , Raymond Josephus Hueting
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/78648
摘要： The invention relates to a method of manufacturing a semiconductor device (1.0) with a dual gate field effect transistor, in which method a semiconductor body (1) of a semiconductor material is provided at a surface thereof with a source region (2) and a drain region (3) of a first conductivity type and with a channel region (4) of a second conductivity type opposite to the first conductivity type between the source region (2) and the drain region (3) and with a first gate region (5) separated from the surface of the semiconductor body by a first gate dielectric (6) above the channel region (4) and with a second gate region (7) situated opposite to the first gate region (5) and formed within a recess (20) in an opposite surface of the semiconductor body (1) so as to be separated from the channel region (4) by a second gate dielectric (8), wherein the recess (20) is formed by means of a local change of the doping (9) of the channel region (4) and by performing an etching step starting from the opposite surface of the semiconductor body (1).
摘要翻译：本发明涉及一种制造具有双栅场效应晶体管的半导体器件（1.0）的方法，其中半导体材料的半导体本体（1）的表面设置有源区（2）和漏极区域（3）和与源极区域（2）和漏极区域（3）之间的第一导电类型相反的第二导电类型的沟道区域（4）和第一栅极区域（ 5）通过沟道区域（4）上方的第一栅极电介质（6）和与第一栅极区域（5）相对并形成在凹槽内的第二栅极区域（7）与半导体本体的表面分离 20）在半导体本体（1）的相对表面中，以便通过第二栅极电介质（8）与沟道区（4）分离，其中凹部（20）通过通道区域（4）的掺杂（9）和从半导体本体（1）的相对表面开始蚀刻步骤。

43. 发明申请

US20070222019A1 Trench Semiconductor Device and Method of Manufacturing it 有权
标题翻译：沟槽半导体器件及其制造方法
公开(公告)号：US20070222019A1
公开(公告)日：2007-09-27
申请号：US10594487
申请日：2005-03-29
申请人： Christelle Rochefort , Erwin Hijzen , Philippe Meunier-Beillard
发明人： Christelle Rochefort , Erwin Hijzen , Philippe Meunier-Beillard
IPC分类号： H01L29/36
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66712 , H01L29/7811
摘要： Consistent with an example embodiment, a reduced surface field effect type (RESURF) semiconductor device is manufactured having a drift region over a drain region. Trenches are formed through openings in mask. A trench insulating layer is deposited on the sidewalls and base of the trenches followed by an overetching step to remove the trench insulating layer from the base of the trenches as well as the top of the sidewalls of the trenches adjacent to the first major surface leaving exposed silicon at the top of the sidewalls of the trench and the base of the trenches. Silicon is selectively grown plugging the trenches with silicon plug (18) leaving void.
摘要翻译：与示例性实施例一致，制造了在漏极区域上具有漂移区域的减小的表面场效应型（RESURF）半导体器件。通过面罩中的开口形成沟槽。沟槽绝缘层沉积在沟槽的侧壁和基底上，随后进行过蚀刻步骤以从沟槽的底部除去沟槽绝缘层以及与第一主表面相邻的沟槽的侧壁的顶部，留下暴露的在沟槽的侧壁的顶部和沟槽的底部的硅。硅被选择性地生长，用硅塞（18）堵塞沟槽，留下空隙。

44. 发明申请

US20060024891A1 Method of manufacture of a trench-gate semiconductor device 有权
标题翻译：沟槽栅极半导体器件的制造方法
公开(公告)号：US20060024891A1
公开(公告)日：2006-02-02
申请号：US10538217
申请日：2003-12-08
申请人： Erwin Hijzen
发明人： Erwin Hijzen
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/7813 , H01L29/42368
摘要： A method of making a trench MOSFET includes forming a layer of porous silicon (26) at the bottom of a trench and then oxidizing the layer of porous silicon (26) to form a plug (30) at the bottom of the trench. This forms a thick oxide plug at the bottom of the trench thereby reducing capacitance between gate and drain.
摘要翻译：制造沟槽MOSFET的方法包括在沟槽的底部形成多孔硅层（26），然后氧化多孔硅层（26），以在沟槽的底部形成插塞（30）。这在沟槽的底部形成厚的氧化物塞，从而减小栅极和漏极之间的电容。

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