专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US09299845B2 Diffusion barrier coated substrates and methods of making the same 有权
标题翻译：扩散阻挡涂层基材及其制备方法
公开(公告)号：US09299845B2
公开(公告)日：2016-03-29
申请号：US12790627
申请日：2010-05-28
申请人： Arvind Kamath , Michael Kocsis , Kevin McCarthy , Gloria Man Ting Wong
发明人： Arvind Kamath , Michael Kocsis , Kevin McCarthy , Gloria Man Ting Wong
IPC分类号： H01L29/786 , H01L27/12
CPC分类号： H01L29/78603 , H01L27/1218 , H01L29/78681 , H01L29/7869
摘要： Semiconductor devices on a diffusion barrier coated metal substrates, and methods of making the same are disclosed. The semiconductor devices include a metal substrate, a diffusion barrier layer on the metal substrate, an insulator layer on the diffusion barrier layer, and a semiconductor layer on the insulator layer. The method includes forming a diffusion barrier layer on the metal substrate, forming an insulator layer on the diffusion barrier layer; and forming a semiconductor layer on the insulator layer. Such diffusion barrier coated substrates prevent diffusion of metal atoms from the metal substrate into a semiconductor device formed thereon.
摘要翻译：公开了扩散阻挡涂层金属基板上的半导体器件及其制造方法。半导体器件包括金属衬底，金属衬底上的扩散阻挡层，扩散阻挡层上的绝缘体层以及绝缘体层上的半导体层。该方法包括在金属基板上形成扩散阻挡层，在扩散阻挡层上形成绝缘体层; 以及在所述绝缘体层上形成半导体层。这种扩散阻挡涂层的基板防止金属原子从金属基板扩散到形成在其上的半导体器件中。

42. 发明授权

US08264359B2 High reliability surveillance and/or identification tag/devices and methods of making and using the same 失效
标题翻译：高可靠性监控和/或识别标签/设备及其制作和使用方法
公开(公告)号：US08264359B2
公开(公告)日：2012-09-11
申请号：US12249754
申请日：2008-10-10
申请人： Vivek Subramanian , Patrick Smith , Vikram Pavate , Arvind Kamath , Criswell Choi , Aditi Chandra , James Montague Cleeves
发明人： Vivek Subramanian , Patrick Smith , Vikram Pavate , Arvind Kamath , Criswell Choi , Aditi Chandra , James Montague Cleeves
IPC分类号： G08B13/14 , G06K19/06
CPC分类号： G08B13/2431 , G06K19/067 , G06K19/07749 , G08B13/242 , G08B13/2437
摘要： The present invention relates to methods of making capacitors for use in surveillance/identification tags or devices, and methods of using such surveillance/identification devices. The capacitors manufactured according to the methods of the present invention and used in the surveillance/identification devices described herein comprise printed conductive and dielectric layers. The methods and devices of the present invention improve the manufacturing tolerances associated with conventional metal-plastic-metal capacitor, as well as the deactivation reliability of the capacitor used in a surveillance/identification tag or device.
摘要翻译：本发明涉及制造用于监视/识别标签或装置的电容器的方法，以及使用这种监视/识别装置的方法。根据本发明的方法制造并用于本文所述的监视/识别装置中的电容器包括印刷的导电和电介质层。本发明的方法和装置改进了与常规金属 - 塑料 - 金属电容器相关的制造公差以及在监视/识别标签或装置中使用的电容器的失活可靠性。

43. 发明授权

US07709307B2 Printed non-volatile memory 有权
标题翻译：打印的非易失性存储器
公开(公告)号：US07709307B2
公开(公告)日：2010-05-04
申请号：US11842884
申请日：2007-08-21
申请人： Arvind Kamath , Patrick Smith , James Montague Cleeves
发明人： Arvind Kamath , Patrick Smith , James Montague Cleeves
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336
CPC分类号： H01L21/28518 , H01L21/288 , H01L21/76801 , H01L21/76895 , H01L27/115 , H01L27/11558 , H01L27/1292 , H01L29/66757 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.
摘要翻译：公开了一种非易失性存储单元，其具有位于相同水平位置并且间隔开预定距离的第一和第二半岛，所述第一半岛具有提供控制栅极和所述第二半岛岛提供源极和漏极端子; 在所述第一半导体岛的至少一部分上的栅介质层; 在所述第二半导体岛的至少一部分上的隧道介电层; 至少部分栅极电介质层和隧道电介质层上的浮栅; 以及与控制栅极以及源极和漏极端子电接触的金属层。在一个有利的实施例中，可以使用“全印刷”工艺技术来制造非易失性存储单元。

44. 发明授权

US07413996B2 High k gate insulator removal 有权
标题翻译：高k栅绝缘子去除
公开(公告)号：US07413996B2
公开(公告)日：2008-08-19
申请号：US10413051
申请日：2003-04-14
申请人： Arvind Kamath , Wai Lo , Venkatesh Gopinath
发明人： Arvind Kamath , Wai Lo , Venkatesh Gopinath
IPC分类号： H01L21/00
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/31122 , H01L29/51 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method of forming a high k gate insulation layer in an integrated circuit on a substrate. A high k layer is deposited onto the substrate, and patterned with a mask to define the high k gate insulation layer and exposed portions of the high k layer. The exposed portions of the high k layer are subjected to an ion implanted species that causes lattice damage to the exposed portions of the high k layer. The lattice damaged exposed portions of the high k layer are etched to leave the high k gate insulation layer.
摘要翻译：在基板上的集成电路中形成高k栅极绝缘层的方法。将高k层沉积在衬底上，并用掩模图案以限定高k栅极绝缘层和高k层的暴露部分。高k层的暴露部分经受离子注入物质，其导致对高k层的暴露部分的晶格损伤。蚀刻高K层的晶格损坏的暴露部分以留下高k栅极绝缘层。

45. 发明申请

US20070007342A1 Methods for manufacturing RFID tags and structures formed therefrom 有权
标题翻译：用于制造由其形成的RFID标签和结构的方法
公开(公告)号：US20070007342A1
公开(公告)日：2007-01-11
申请号：US11452108
申请日：2006-06-12
申请人： James Cleeves , J. MacKenzie , Arvind Kamath
发明人： James Cleeves , J. MacKenzie , Arvind Kamath
IPC分类号： G06K7/00 , G08B13/14
CPC分类号： H01L27/1255 , G06K19/073 , G06K19/07749 , H01F17/0006 , H01L23/13 , H01L23/142 , H01L23/66 , H01L27/127 , H01L27/1292 , H01L28/60 , H01L29/66143 , H01L29/66742 , H01L29/78696 , H01L29/872 , H01L2223/6611 , H01L2223/6677 , H01L2924/0002 , H01L2924/00
摘要： Radio frequency identification (RFID) tags and processes for manufacturing the same. The RFID device generally includes (1) a metal antenna and/or inductor; (2) a dielectric layer thereon, to support and insulate integrated circuitry from the metal antenna and/or inductor; (3) a plurality of diodes and a plurality of transistors on the dielectric layer, the diodes having at least one layer in common with the transistors; and (4) a plurality of capacitors in electrical communication with the metal antenna and/or inductor and at least some of the diodes, the plurality of capacitors having at least one layer in common with the plurality of diodes and/or with contacts to the diodes and transistors. The method preferably integrates liquid silicon-containing ink deposition into a cost effective, integrated manufacturing process for the manufacture of RFID circuits. Furthermore, the present RFID tags generally provide higher performance (e.g., improved electrical characteristics) as compared to tags containing organic electronic devices.
摘要翻译：射频识别（RFID）标签及其制造方法。 RFID设备通常包括（1）金属天线和/或电感器; （2）其上的介电层，用于支撑和绝缘来自金属天线和/或电感器的集成电路; （3）介电层上的多个二极管和多个晶体管，二极管具有至少一个与晶体管共同的层; 和（4）与金属天线和/或电感器以及至少一些二极管电连通的多个电容器，所述多个电容器具有与所述多个二极管共同的至少一个层和/或与所述多个二极管的触点二极管和晶体管。该方法优选将液态含硅油墨沉积物集成到用于制造RFID电路的成本有效的集成制造工艺中。此外，与含有机电子器件的标签相比，本RFID标签通常提供更高的性能（例如，改进的电气特性）。

46. 发明申请

US20050006347A1 Hard mask removal 有权
标题翻译：硬面膜去除
公开(公告)号：US20050006347A1
公开(公告)日：2005-01-13
申请号：US10615558
申请日：2003-07-08
申请人： Venkatesh Gopinath , Arvind Kamath , Mohammad Mirabedini , Ming-Yi Lee , Brian Baylis
发明人： Venkatesh Gopinath , Arvind Kamath , Mohammad Mirabedini , Ming-Yi Lee , Brian Baylis
IPC分类号： H01L21/311 , C23F1/00
CPC分类号： H01L21/31144 , H01L21/31116
摘要： A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.
摘要翻译：从形成在下层上的图案化层去除硬掩模层的方法，其中使用蚀刻剂去除硬掩模层，当底层在通常需要的时间长时间暴露于蚀刻剂时不利地蚀刻下面的层以去除硬掩模层，而不会有害地蚀刻下面的层。修改硬掩模层，使得蚀刻剂以比蚀刻剂蚀刻下层的蚀刻剂快得多的速率蚀刻硬掩模层。图案化硬掩模层。蚀刻图案层以暴露下层的部分。硬掩模层和下层的暴露部分用蚀刻剂蚀刻，其中蚀刻剂以比蚀刻剂蚀刻下层的速率快得多的速度蚀刻硬掩模层，这是因为硬的掩模层。

47. 发明授权

US06687114B1 High density memory with storage capacitor 有权
标题翻译：具有存储电容器的高密度存储器
公开(公告)号：US06687114B1
公开(公告)日：2004-02-03
申请号：US10403433
申请日：2003-03-31
申请人： Arvind Kamath , Ruggero Castagnetti
发明人： Arvind Kamath , Ruggero Castagnetti
IPC分类号： H01G4228
CPC分类号： H01L27/1087 , H01L27/10894 , H01L29/66181
摘要： A memory cell having a transistor and a capacitor formed in a silicon substrate. The capacitor is formed with a lower electrically conductive plate etched in a projected surface area of the silicon substrate. The lower electrically conductive plate has at least one cross section in the shape of a vee, where the sides of the vee are disposed at an angle of about fifty-five degrees from a top surface of the silicon substrate. The surface area of the lower electrically conductive plate is about seventy-three percent larger than the projected surface area of the silicon substrate in which the lower electrically conductive plate is etched. A capacitor dielectric layer is formed of a first deposited dielectric layer, which is disposed adjacent the lower electrically conductive plate. A top electrically conductive plate is disposed adjacent the capacitor dielectric layer and opposite the lower electrically conductive plate. A transistor is formed having source and drain regions separated by a channel region, and a gate dielectric layer formed of the first deposited dielectric layer.
摘要翻译：具有在硅衬底中形成的晶体管和电容器的存储单元。电容器形成有在硅衬底的投影表面区域中蚀刻的下导电板。下导电板具有至少一个vee形状的横截面，其中，vee的侧面与硅衬底的顶表面成约五十五度的角度。下导电板的表面积比其中蚀刻下导电板的硅衬底的投影表面积大约百分之七点三。电容器介电层由邻近下导电板设置的第一沉积介电层形成。顶部导电板设置在电容器电介质层附近并与下部导电板相对。晶体管形成为具有由沟道区域分离的源极和漏极区域以及由第一沉积介电层形成的栅极电介质层。

48. 发明授权

US11916192B2 Multilayer solid-state electrolyte, battery cells including the same, and methods of making the same 有权
公开(公告)号：US11916192B2
公开(公告)日：2024-02-27
申请号：US17185159
申请日：2021-02-25
申请人： Zhongchun Wang , Arvind Kamath
发明人： Zhongchun Wang , Arvind Kamath
IPC分类号： H01M10/0562 , H01M10/0525 , H01M10/0585 , H01M4/62 , H01M4/36 , H01M4/02
CPC分类号： H01M10/0562 , H01M4/366 , H01M4/62 , H01M10/0525 , H01M10/0585 , H01M2004/027 , H01M2300/0071 , H01M2300/0094
摘要： A multilayer solid-state electrolyte, solid-state battery cells including the same, and methods of making the electrolyte and the battery cells are disclosed. The multi-layer solid-state electrolyte includes a solid bulk electrolyte layer comprising carbon-doped lithium phosphorus oxynitride (LiPON) or WO3+x (where 0≤x≤1), and a solid anode interface layer comprising LiPON or a metal oxide that forms a stable complex oxide with lithium oxide and conducts lithium ions when lithiated. The anode interface layer has a thickness less than that of the bulk electrolyte layer. The method of making the multi-layer solid-state electrolyte includes depositing one of the solid bulk electrolyte layer and the solid anode interface layer on an active layer of a battery cell, then depositing the other layer on the one layer. As for the solid-state electrolyte, the anode interface layer has a thickness less than that of the bulk electrolyte layer.

49. 发明授权

US11735791B2 Solid-state battery and method of making the same 有权
公开(公告)号：US11735791B2
公开(公告)日：2023-08-22
申请号：US17185111
申请日：2021-02-25
申请人： Richard Van Der Linde , Aditi Chandra , Mao Ito , Alex Yan , Arvind Kamath , Shoba Rao , Jonathon Y Simmons
发明人： Richard Van Der Linde , Aditi Chandra , Mao Ito , Alex Yan , Arvind Kamath , Shoba Rao , Jonathon Y Simmons
IPC分类号： H01M10/058 , H01M50/186
CPC分类号： H01M50/186 , H01M10/058
摘要： The present disclosure pertains to a battery and a method of making the same. The battery includes first and second metal substrates, a first solid-state and/or thin-film battery cell on the first metal substrate, a second solid-state and/or thin-film battery cell on the second metal substrate, and a hermetic seal in a peripheral region of the first and second metal substrates. The first and second battery cells are between the first and second metal substrates, and face each other. The method includes respectively forming first and second solid-state and/or thin-film battery cells on first and second metal substrates, placing the second battery cell on the first battery cell so that the first and second battery cells are between the first and second metal substrates, and hermetically sealing the first and second battery cells in a peripheral region of the first and second metal substrates.

50. 发明授权

US09183973B2 Diffusion barrier coated substrates and methods of making the same 有权
标题翻译：扩散阻挡涂层基材及其制备方法
公开(公告)号：US09183973B2
公开(公告)日：2015-11-10
申请号：US13873156
申请日：2013-04-29
申请人： Arvind Kamath , Michael Kocsis , Kevin McCarthy , Gloria Wong , Jiang Li
发明人： Arvind Kamath , Michael Kocsis , Kevin McCarthy , Gloria Wong , Jiang Li
IPC分类号： H01F5/00 , H01Q7/00 , H01L29/786 , H01L27/12 , H01Q1/22 , H01F41/04
CPC分类号： H01F5/003 , H01F5/00 , H01F41/041 , H01L27/1218 , H01L27/1292 , H01L29/78603 , H01L29/78681 , H01L29/7869 , H01Q1/2283 , H01Q7/00
摘要： Devices on a diffusion barrier coated metal substrates, and methods of making the same are disclosed. The devices include a metal substrate, a diffusion barrier layer on the metal substrate, one or more insulator layers on the diffusion barrier layer, and an antenna and/or inductor on the one or more insulator layer(s). The method includes forming a diffusion barrier layer on the metal substrate, forming one or more insulator layers on the diffusion barrier layer; and forming an antenna and/or inductor on an uppermost one of the insulator layer(s). The antenna and/or inductor is electrically connected to at least one of the diffusion barrier layer and/or the metal substrate. Such diffusion barrier coated substrates prevent diffusion of metal atoms from the metal substrate into device layers formed thereon.
摘要翻译：公开了扩散阻挡涂层金属基板上的器件及其制造方法。这些器件包括金属衬底，金属衬底上的扩散阻挡层，扩散阻挡层上的一个或多个绝缘体层，以及一个或多个绝缘体层上的天线和/或电感器。该方法包括在金属基板上形成扩散阻挡层，在扩散阻挡层上形成一个或多个绝缘体层; 以及在所述绝缘体层的最上面形成天线和/或电感器。天线和/或电感器电连接到扩散阻挡层和/或金属基底中的至少一个。这种扩散阻挡涂层的基底防止金属原子从金属基底扩散到其上形成的器件层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式