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41. 发明授权

US5504760A Mixed data encoding EEPROM system 失效
标题翻译：混合数据编码EEPROM系统
公开(公告)号：US5504760A
公开(公告)日：1996-04-02
申请号：US148930
申请日：1993-11-08
申请人： Eliyahou Harari , Daniel C. Guterman , Sanjay Mehrotra , Stephen J. Gross , Robert D. Norman
发明人： Eliyahou Harari , Daniel C. Guterman , Sanjay Mehrotra , Stephen J. Gross , Robert D. Norman
IPC分类号： G06F11/10 , G11C16/10 , G11C16/16 , G11C16/26
CPC分类号： G11C16/10 , G11C16/16 , G11C16/26 , G06F11/1008
摘要： In a mixed data encoding scheme for programming data into a flash sector of a flash EEPROM system, a method for determining which data encoding scheme has been used for programming the retrieved data involves examining whether an error correction code of the data indicates an error.
摘要翻译：在用于将数据编程到闪存EEPROM系统的闪存扇区中的混合数据编码方案中，确定已经使用哪种数据编码方案来编程检索的数据的方法涉及检查数据的纠错码是否指示错误。

42. 发明授权

US5396468A Streamlined write operation for EEPROM system 失效
标题翻译： EEPROM系统的简化写操作
公开(公告)号：US5396468A
公开(公告)日：1995-03-07
申请号：US148932
申请日：1993-11-08
申请人： Eliyahou Harari , Daniel C. Guterman , Sanjay Mehrotra , Stephen J. Gross , John S. Mangan
发明人： Eliyahou Harari , Daniel C. Guterman , Sanjay Mehrotra , Stephen J. Gross , John S. Mangan
IPC分类号： G06F11/10 , G11C16/10 , G11C16/16 , G11C16/26 , G11C7/00
CPC分类号： G11C16/10 , G11C16/16 , G11C16/26 , G06F11/1008
摘要： Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM). An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses. Techniques include a 2-phase verification process interleaving between pulse applications; special handling of a sample of cells within each erasable unit group; defects handling; and adaptive initial erasing voltages. A streamlined write operation on a flash sector of the EEPROM is implemented by employing the optimized erase in an efficient manner. The write operation includes an initial quick erase of the sector followed by programming of data and verification. Only on those infrequent occasions when a failure occurs as manifested during program verification that the optimized erase will need be evoked.
摘要翻译：各种优化技术用于擦除半导体电可擦除可编程只读存储器（EEPROM）。擦除算法通过应用增量擦除脉冲来实现一组存储器单元的擦除。技术包括脉冲应用之间的两相验证过程交错; 对每个可擦除单元组内的单元格样本进行特殊处理; 缺陷处理; 和自适应初始擦除电压。通过以有效的方式采用优化的擦除来实现EEPROM的闪存扇区上的流线型写入操作。写入操作包括扇区的初始快速擦除，然后对数据进行编程和验证。只有当程序验证中出现故障时才会发现需要引发优化的擦除。

43. 发明授权

US06977844B2 Method of reducing disturbs in non-volatile memory 失效
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：US06977844B2
公开(公告)日：2005-12-20
申请号：US11054084
申请日：2005-02-08
申请人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C16/02 , G11C16/12 , G11C16/04
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

44. 发明授权

US06888752B2 Method of reducing disturbs in non-volatile memory 有权
公开(公告)号：US06888752B2
公开(公告)日：2005-05-03
申请号：US10613098
申请日：2003-07-01
申请人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C16/02 , G11C16/12 , G11C16/04
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

45. 发明授权

US06717851B2 Method of reducing disturbs in non-volatile memory 有权
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：US06717851B2
公开(公告)日：2004-04-06
申请号：US09759835
申请日：2001-01-10
申请人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C1604
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

46. 发明授权

US07468915B2 Method of reducing disturbs in non-volatile memory 有权
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：US07468915B2
公开(公告)日：2008-12-23
申请号：US11538521
申请日：2006-10-04
申请人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C11/34
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

47. 发明授权

US06570785B1 Method of reducing disturbs in non-volatile memory 有权
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：US06570785B1
公开(公告)日：2003-05-27
申请号：US09703083
申请日：2000-10-31
申请人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang
发明人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang
IPC分类号： G11C1610
CPC分类号： G11C16/12
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage is adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

48. 发明授权

US07145804B2 Method of reducing disturbs in non-volatile memory 有权
公开(公告)号：US07145804B2
公开(公告)日：2006-12-05
申请号：US11238911
申请日：2005-09-28
申请人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C11/34
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

49. 发明授权

US07916552B2 Tracking cells for a memory system 有权
标题翻译：跟踪单元格的内存系统
公开(公告)号：US07916552B2
公开(公告)日：2011-03-29
申请号：US12763569
申请日：2010-04-20
申请人： Daniel C. Guterman , Stephen J. Gross , Shazad Khalid , Geoffrey S. Gongwer
发明人： Daniel C. Guterman , Stephen J. Gross , Shazad Khalid , Geoffrey S. Gongwer
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5621 , G11C16/349
摘要： Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.
摘要翻译：在存储器系统中使用跟踪单元来改善读取过程。跟踪单元可以提供数据质量的指示，如果存在错误，可以将其用作数据恢复操作的一部分。跟踪单元提供了将读取参数调整到最佳水平以便反映存储器系统的当前状况的手段。另外，使用多状态存储器单元的一些存储器系统将应用旋转数据方案以最小化磨损。可以基于多个跟踪单元的状态在跟踪单元中编码旋转方案，该单元在读取时被解码。

50. 发明授权

US07848149B2 Reducing the effects of noise in non-volatile memories through multiple reads 有权
标题翻译：通过多次读取降低非易失性存储器中噪声的影响
公开(公告)号：US07848149B2
公开(公告)日：2010-12-07
申请号：US11674000
申请日：2007-02-12
申请人： Carlos J. Gonzalez , Daniel C. Guterman
发明人： Carlos J. Gonzalez , Daniel C. Guterman
IPC分类号： G11C11/34
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1051 , G11C16/12 , G11C16/26 , G11C16/28 , G11C16/3454 , G11C16/3459 , G11C2013/0057
摘要： Storage elements are read multiple times and the results are accumulated and averaged for each storage element to reduce the effects of noise or other transients in the storage elements and associated circuits that may adversely affect the quality of the read. Several techniques may be employed, including: A full read and transfer of the data from the storage device to the controller device for each iteration, with averaging performed by the controller; a full read of the data for each iteration, with the averaging performed by the storage device, and no transfer to the controller until the final results are obtained; one full read followed by a number of faster re-reads exploiting the already established state information to avoid a full read, followed by an intelligent algorithm to guide the state at which the storage element is sensed. These techniques may be used as the normal mode of operation, or invoked upon exception condition, depending on the system characteristics. A similar form of signal averaging may be employed during the verify phase of programming. An embodiment of this technique would use a peak-detection scheme. In this scenario, several verify checks are performed at the state prior to deciding if the storage element has reached the target state. If some predetermined portion of the verifies fail, the storage element receives additional programming. These techniques allow the system to store more states per storage element in the presence of various sources of noise.
摘要翻译：存储元件被读取多次，并且对于每个存储元件累积和平均结果，以减少可能不利地影响读取质量的存储元件和相关电路中的噪声或其他瞬变的影响。可以采用几种技术，其中包括：由控制器对平均数据进行每次迭代从存储设备到控制器设备的完整读取和传输; 对每次迭代的数据进行完全读取，并由存储设备进行平均，并且在获得最终结果之前不转移到控制器; 一次完全读取，然后利用已建立的状态信息进行多次更快的重新读取，以避免完全读取，随后是引导存储元件被感测的状态的智能算法。这些技术可以用作正常操作模式，或者根据异常情况被调用，这取决于系统特性。可以在编程的验证阶段期间采用类似形式的信号平均。该技术的实施例将使用峰值检测方案。在这种情况下，在决定存储元件是否达到目标状态之前，先在状态下执行多个验证检查。如果验证的一些预定部分失败，则存储元件接收另外的编程。这些技术允许系统在存在各种噪声源的情况下存储每个存储元件的更多状态。

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