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41. 发明申请

US20130065370A1 Method for Fabricating Field Effect Transistor Devices with High-Aspect Ratio Mask 失效
标题翻译：制造具有高比例掩模的场效应晶体管器件的方法
公开(公告)号：US20130065370A1
公开(公告)日：2013-03-14
申请号：US13229154
申请日：2011-09-09
申请人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L21/28273 , H01L29/66825 , H01L29/785
摘要： A method for forming feature on a substrate includes forming at least one layer of a feature material on a substrate, patterning a photolithographic resist material on the at least one layer of the feature material, removing portions of the feature material to define a feature, depositing a masking material layer over the resist material and exposed regions of the substrate, modifying a portion of the substrate, and removing the masking material layer and the resist material.
摘要翻译：在衬底上形成特征的方法包括在衬底上形成至少一层特征材料，在特征材料的至少一层上图案化光刻抗蚀剂材料，去除特征材料的部分以限定特征，沉积在抗蚀剂材料上的掩模材料层和衬底的暴露区域，修改衬底的一部分，以及去除掩模材料层和抗蚀剂材料。

42. 发明申请

US20130043535A1 ISOLATION REGION FABRICATION FOR REPLACEMENT GATE PROCESSING 有权
标题翻译：用于替代浇口加工的隔离区制造
公开(公告)号：US20130043535A1
公开(公告)日：2013-02-21
申请号：US13213713
申请日：2011-08-19
申请人： Brent A. Anderson , Edward J. Nowak
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L21/762 , H01L27/12
CPC分类号： H01L29/66545 , H01L21/28123 , H01L21/76283 , H01L21/84
摘要： A method for isolation region fabrication for replacement gate integrated circuit (IC) processing includes forming a plurality of dummy gates on a substrate; forming a block mask over the plurality of dummy gates, such that the block mask selectively exposes a dummy gate of the plurality of dummy gates; removing the exposed dummy gate to form an isolation region recess corresponding to the removed dummy gate; filling the isolation region recess with an insulating material to form an isolation region; removing the block mask to expose a remaining plurality of dummy gates; and performing replacement gate processing on the remaining plurality of dummy gates to form a plurality of active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region.
摘要翻译：用于替换栅极集成电路（IC）处理的隔离区域制造的方法包括在衬底上形成多个虚拟栅极; 在所述多个虚拟栅极上形成块掩模，使得所述块掩模选择性地暴露所述多个伪栅极的伪栅极; 去除所暴露的虚拟栅极以形成对应于去除的虚拟栅极的隔离区域凹部; 用绝缘材料填充隔离区域凹部以形成隔离区域; 去除所述块掩模以暴露剩余的多个伪栅极; 以及对剩余的多个伪栅极执行替换栅极处理以形成多个有源器件，其中所述多个有源器件中的至少两个通过所述隔离区域彼此电隔离。

43. 发明授权

US08350343B2 Field effect transistor with channel region edge and center portions having different band structures for suppressed corner leakage 有权
标题翻译：场效应晶体管，沟道区域边缘和中心部分具有不同的带结构，用于抑制拐角泄漏
公开(公告)号：US08350343B2
公开(公告)日：2013-01-08
申请号：US13362019
申请日：2012-01-31
申请人： Brent A. Anderson , Edward J. Nowak
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L29/76
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823878 , H01L29/0661 , H01L29/1037 , H01L29/42376 , H01L29/517 , H01L29/785
摘要： Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs.
摘要翻译：作为通道材料带边调制的函数，公开了具有抑制的副阈值拐角泄漏的场效应晶体管（FET）的实施例。具体地说，与中心相比，FET沟道区在边缘形成不同的材料。选择具有不同带结构和这些材料的特定位置的不同材料，以便有效地提高沟道区域相对于沟道区域中心处的Vt的边缘处的阈值电压（Vt），从而抑制子阈值角泄漏。还公开了用于这种FET的设计结构和用于形成这种FET的方法实施例。

44. 发明申请

US20120208329A1 INTEGRATED CIRCUIT DEVICE WITH SERIES-CONNECTED FIELD EFFECT TRANSISTORS AND INTEGRATED VOLTAGE EQUALIZATION AND METHOD OF FORMING THE DEVICE 失效
标题翻译：具有串联场效应晶体管和集成电压均衡的集成电路装置及其形成方法
公开(公告)号：US20120208329A1
公开(公告)日：2012-08-16
申请号：US13455176
申请日：2012-04-25
申请人： Andres Bryant , Edward J. Nowak
发明人： Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/84 , H01L21/8234
CPC分类号： H01L21/845 , H01L21/84 , H01L27/1203 , H01L27/1211
摘要： Disclosed is an integrated circuit device having series-connected planar or non-planar field effect transistors (FETs) with integrated voltage equalization and a method of forming the device. The series-connected FETs comprise gates positioned along a semiconductor body to define the channel regions for the series-connected FETs. Source/drain regions are located within the semiconductor body on opposing sides of the channel regions such that each portion of the semiconductor body between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor. Integrated voltage equalization is achieved through a conformal conductive layer having a desired resistance and positioned over the series-connected FETs such that it is electrically isolated from the gates, but in contact with the source/drain regions within the semiconductor body.
摘要翻译：公开了具有集成电压均衡的具有串联的平面或非平面场效应晶体管（FET）的集成电路器件和形成器件的方法。串联连接的FET包括沿着半导体本体定位的门，以限定用于串联连接的FET的沟道区。源极/漏极区域位于沟道区域的相对侧上的半导体本体内，使得相邻栅极之间的半导体本体的每个部分包括用于一个场效应晶体管的一个源极/漏极区域，用于与另一个场效应晶体管的另一个源极/漏极区域相邻接。集成电压均衡通过具有期望电阻的并行导电层实现，并且位于串联连接的FET上，使得其与栅极电隔离，但与半导体本体内的源极/漏极区域接触。

45. 发明授权

US08234594B2 Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same 有权
标题翻译：冗余微环结构用于集成电路物理设计过程及其形成方法
公开(公告)号：US08234594B2
公开(公告)日：2012-07-31
申请号：US11552225
申请日：2006-10-24
申请人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
发明人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
IPC分类号： G06F17/50 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located at a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is approximately axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is approximately axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.
摘要翻译：一种集成电路，包括第一级布线轨道的第一线，第二级布线轨道的第二线，第三级布线轨道的第三线和位于距离第二线的第一距离的第四线在第二级线路上。第一通孔在第二导线的第一位置连接第一和第二导线。第二通孔在第一位置处连接第二和第三导线，第二通孔大致轴向对准第一通孔。第三通过在第四线的第二位置连接第三和第四导线。在第二位置连接第一和第四导线的第四通孔，第四通孔与第三通孔大致轴向对齐。第二，第三和第四通孔以及第三和第四导线形成第一和第二导线之间的路径，该路径对于第一通孔是冗余的。

46. 发明授权

US08232627B2 Integrated circuit device with series-connected field effect transistors and integrated voltage equalization and method of forming the device 有权
标题翻译：具有串联场效应晶体管和集成电压均衡的集成电路器件及其形成方法
公开(公告)号：US08232627B2
公开(公告)日：2012-07-31
申请号：US12563195
申请日：2009-09-21
申请人： Andres Bryant , Edward J. Nowak
发明人： Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/06
CPC分类号： H01L21/845 , H01L21/84 , H01L27/1203 , H01L27/1211
摘要： Disclosed is an integrated circuit device having series-connected planar or non-planar field effect transistors (FETs) with integrated voltage equalization and a method of forming the device. The series-connected FETs comprise gates positioned along a semiconductor body to define the channel regions for the series-connected FETs. Source/drain regions are located within the semiconductor body on opposing sides of the channel regions such that each portion of the semiconductor body between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor. Integrated voltage equalization is achieved through a conformal conductive layer having a desired resistance and positioned over the series-connected FETs such that it is electrically isolated from the gates, but in contact with the source/drain regions within the semiconductor body.
摘要翻译：公开了具有集成电压均衡的具有串联的平面或非平面场效应晶体管（FET）的集成电路器件和形成器件的方法。串联连接的FET包括沿着半导体本体定位的门，以限定用于串联连接的FET的沟道区。源极/漏极区域位于沟道区域的相对侧上的半导体本体内，使得相邻栅极之间的半导体本体的每个部分包括用于一个场效应晶体管的一个源极/漏极区域，用于与另一个场效应晶体管的另一个源极/漏极区域相邻接。集成电压均衡通过具有期望电阻的并行导电层实现，并且位于串联连接的FET上，使得其与栅极电隔离，但与半导体本体内的源极/漏极区域接触。

47. 发明申请

US20120181588A1 PIXEL SENSOR CELLS WITH A SPLIT-DIELECTRIC TRANSFER GATE 失效
标题翻译：具有分离电介质转移栅的像素传感器电池
公开(公告)号：US20120181588A1
公开(公告)日：2012-07-19
申请号：US13005650
申请日：2011-01-13
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L31/113 , G06F17/50 , H01L31/18
CPC分类号： H01L27/14614 , H01L27/14689
摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. A transistor in the pixel sensor cell has a gate structure that includes a gate dielectric with a thick region and a thin region. A gate electrode of the gate structure is formed on the thick region of the gate dielectric and the thin region of the gate dielectric. The thick region of the gate dielectric and the thin region of the gate dielectric provide the transistor with an asymmetric threshold voltage.
摘要翻译：像素传感器单元，制造像素传感器单元的方法以及像素传感器单元的设计结构。像素传感器单元中的晶体管具有包括具有厚区域和薄区域的栅极电介质的栅极结构。栅极结构的栅电极形成在栅极电介质的厚区域和栅极电介质的薄区域上。栅极电介质的厚区域和栅极电介质的薄区为晶体管提供非对称阈值电压。

48. 发明申请

US20120168873A1 TRANSMISSION GATES WITH ASYMMETRIC FIELD EFFECT TRANSISTORS 审中-公开
标题翻译：具有不对称场效应晶体管的传输门
公开(公告)号：US20120168873A1
公开(公告)日：2012-07-05
申请号：US12984773
申请日：2011-01-05
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/70 , G06F17/50 , H01L21/8238
CPC分类号： H01L27/0922 , H01L21/26586 , H01L21/823807 , H01L29/66659
摘要： Transmission gates, methods of fabricating transmission gates, and design structures for a transmission gate. The transmission gate includes an n-channel field effect transistor characterized by terminals that are asymmetrically doped and a p-channel field effect transistor characterized by terminals that are asymmetrically doped.
摘要翻译：传输门，制造传输门的方法和传输门的设计结构。传输门包括n沟道场效应晶体管，其特征在于不对称掺杂的端子和由不对称掺杂的端子表征的p沟道场效应晶体管。

49. 发明申请

US20120156838A1 MULTI-GATE NON-PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD OF FORMING THE STRUCTURE USING A DOPANT IMPLANT PROCESS TO TUNE DEVICE DRIVE CURRENT 有权
标题翻译：多栅极非平面场效应晶体管结构和使用DOPANT IMPLANT工艺形成结构以调节器件驱动电流的方法
公开(公告)号：US20120156838A1
公开(公告)日：2012-06-21
申请号：US13406652
申请日：2012-02-28
申请人： Brent A. Anderson , Edward J. Nowak
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L21/8238
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： Disclosed are embodiments of a semiconductor structure that includes one or more multi-gate field effect transistors (MUGFETs), each MUGFET having one or more semiconductor fins. In the embodiments, dopant implant region is incorporated into the upper portion of the channel region of a semiconductor fin in order to selectively modify (i.e., decrease or increase) the threshold voltage within that upper portion relative to the threshold voltage in the lower portion and, thereby to selectively modify (i.e., decrease or increase) device drive current. In the case of a multiple semiconductor fins, the use of implant regions, the dopant conductivity type in the implant regions and/or the sizes of the implant regions can be varied from fin to fin within a multi-fin MUGFET or between different single and/or multi-fin MUGFETs so that individual device drive current can be optimized. Also disclosed herein are embodiments of a method of forming the semiconductor structure.
摘要翻译：公开了包括一个或多个多栅极场效应晶体管（MUGFET）的半导体结构的实施例，每个MUGFET具有一个或多个半导体鳍片。在实施例中，掺杂剂注入区域被并入到半导体鳍片的沟道区域的上部，以便相对于下部的阈值电压选择性地修改（即，降低或增加）该上部内的阈值电压），从而选择性地修改（即，减小或增加）器件驱动电流。在多个半导体鳍片的情况下，注入区域，植入区域中的掺杂剂导电类型和/或植入区域的尺寸的使用可以在多翅片MUGFET内的翅片或鳍片之间或者在不同的单个和 /或多鳍MUGFET，使得可以优化单个设备驱动电流。本文还公开了形成半导体结构的方法的实施例。

50. 发明申请

US20120098066A1 SIMULTANEOUS FORMATION OF FINFET AND MUGFET 有权
标题翻译：同时形成FINFET和MUGFET
公开(公告)号：US20120098066A1
公开(公告)日：2012-04-26
申请号：US12909917
申请日：2010-10-22
申请人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L29/786 , H01L21/336 , H01L21/311
CPC分类号： H01L29/7855 , H01L21/3081 , H01L29/66795 , H01L29/785
摘要： A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure position on a substrate. The first rectangular fin structure has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The structure additionally includes a second rectangular fin structure position on the substrate. Similarly, the second rectangular fin structure also has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench insulator is positioned on the substrate and is positioned between a side of the first rectangular fin structure and a side of the second rectangular fin structure. Additionally, a gate conductor is positioned on the trench insulator, positioned over the sides and the top of the first rectangular fin structure, and positioned over the sides and the top of the second rectangular fin structure. The gate conductor runs perpendicular to the sides of the first rectangular fin structure and the sides of the second rectangular fin structure. Also, a gate insulator is positioned between the gate conductor and the first rectangular fin structure and between the gate conductor and the second rectangular fin structure. The structure further includes a first cap on the top of the first rectangular fin structure. The first cap separates the gate conductor from the first rectangular fin structure.
摘要翻译：一种方法和结构包括场效应晶体管结构，其包括在衬底上的第一矩形鳍结构位置。第一矩形翅片结构具有接触基底的底部，与底部相对的顶部以及顶部和底部之间的边。该结构还包括在基底上的第二矩形翅片结构位置。类似地，第二矩形翅片结构还具有接触基底的底部，与底部相对的顶部以及顶部和底部之间的边。第二矩形翅片结构的侧面平行于第一矩形翅片结构的侧面。此外，沟槽绝缘体位于衬底上并且位于第一矩形翅片结构的侧面和第二矩形鳍结构的侧面之间。此外，栅极导体位于沟槽绝缘体上，位于第一矩形翅片结构的侧面和顶部之上，并且位于第二矩形鳍结构的侧面和顶部之上。栅极导体垂直于第一矩形翅片结构的侧面和第二矩形翅片结构的侧面延伸。此外，栅极绝缘体位于栅极导体和第一矩形翅片结构之间以及栅极导体和第二矩形鳍结构之间。该结构还包括在第一矩形翅片结构的顶部上的第一盖。第一盖将栅极导体与第一矩形鳍结构分开。

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