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41. 发明授权

US07479683B2 Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics 失效
标题翻译：在具有高k电介质的CMOS器件制造中实现势垒层的选择性实现以实现阈值电压控制
公开(公告)号：US07479683B2
公开(公告)日：2009-01-20
申请号：US10957342
申请日：2004-10-01
申请人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L29/513 , H01L21/28079 , H01L21/28088 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first stack of a pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET device is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.
摘要翻译：本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。该结构还包括位于一些器件通道顶部的pFET器件的第一堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

42. 发明申请

US20090011610A1 SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE TRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH K DIELECTRICS 有权
标题翻译：采用高K电介质的CMOS器件制造中实现栅极电压控制的障碍层的选择性实现
公开(公告)号：US20090011610A1
公开(公告)日：2009-01-08
申请号：US12211530
申请日：2008-09-16
申请人： Nestor A. Bojarczuk, JR. , Cyril Cabral, JR. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Nestor A. Bojarczuk, JR. , Cyril Cabral, JR. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L21/31
CPC分类号： H01L29/513 , H01L21/28079 , H01L21/28088 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.
摘要翻译：一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在所述半导体衬底上形成包括在高k电介质顶上的绝缘夹层的电介质叠层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极堆叠。绝缘中间层可以是AlN或AlOxNy。高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。可以通过包括HCl / H2O2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

43. 发明申请

US20080308872A1 CMOS TRANSISTORS WITH DIFFERENTIAL OXYGEN CONTENT HIGH-K DIELECTRICS 失效
标题翻译：具有差分氧含量高K电介质的CMOS晶体管
公开(公告)号：US20080308872A1
公开(公告)日：2008-12-18
申请号：US11763047
申请日：2007-06-14
申请人： Huiming Bu , Eduard A. Cartier , Bruce B. Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
发明人： Huiming Bu , Eduard A. Cartier , Bruce B. Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823864 , H01L21/823814 , H01L21/823857 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/4908 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.
摘要翻译：在半导体衬底上形成包含第一高k电介质部分的NFET和包含第二高k栅极电介质部分的PFET。栅极侧壁氮化物形成在NFET的栅极上，而PFET的侧壁保持没有栅极侧壁氮化物。直接在PFET栅极堆叠的侧壁上和NFET上的栅极侧壁氮化物上形成氧化物间隔物。在高温处理之后，第一和第二介质部分含有非化学计量的缺氧高k电介质材料。半导体结构在氧气环境中进行退火，在该环境中，氧气通过氧化物间隔物扩散到第二高k电介质部分。 PFET包括更高化学计量的高k电介质材料，并且NFET包含较少化学计量的高k电介质材料。本发明优化了PFET和NFET的阈值电压。

44. 发明授权

US07242055B2 Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide 失效
标题翻译：包含通过沉积金属氧化物形成的阈值电压控制层的含氮场效应晶体管栅叠层
公开(公告)号：US07242055B2
公开(公告)日：2007-07-10
申请号：US10988733
申请日：2004-11-15
申请人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Paul C. Jamison , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Paul C. Jamison , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L29/792
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/2822 , H01L21/823828 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/517 , H01L29/518
摘要： A semiconductor structure is provided that includes a Vt stabilization layer between a gate dielectric and a gate electrode. The Vt stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the proviso that when the Vt stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.
摘要翻译：提供了一种半导体结构，其包括在栅极电介质和栅电极之间的V 1稳定层。 VST稳定层能够将结构的阈值电压和平带电压稳定到目标值，并且包括氮化金属氧化物或无氮金属氧化物，条件是当V < 稳定层包括无氮金属氧化物，半导体衬底或栅极电介质中的至少一个包括氮。本发明还提供一种制造这种结构的方法。

45. 发明授权

US06326732B1 Apparatus and method for non-contact stress evaluation of wafer gate dielectric reliability 有权
标题翻译：晶圆栅介质可靠性非接触应力评估装置及方法
公开(公告)号：US06326732B1
公开(公告)日：2001-12-04
申请号：US09250880
申请日：1999-02-16
申请人： Wagdi W. Abadeer , Eduard A. Cartier , James H. Stathis
发明人： Wagdi W. Abadeer , Eduard A. Cartier , James H. Stathis
IPC分类号： H01J724
CPC分类号： G01R31/2623 , G01R31/275
摘要： An apparatus and method for evaluating the performance of a test dielectric material for use as a gate dielectric. The method comprises exposing a coated layer of the dielectric to a concentration of atomic hydrogen. The method may comprise (a) measuring an initial value of interface-state density in the test dielectric, (b) exposing the coated test dielectric to a concentration of atomic hydrogen in a remote plasma, and then (c) measuring a post-exposure value of interface-state density in the test dielectric. Steps (b) and (c) may be repeated with incrementally higher concentrations of atomic hydrogen to determine a rate of change in interface-state density value as a function of atomic hydrogen concentration, which may then be related to the projected charge-to-breakdown or time-to-breakdown of the test dielectric layer when the dielectric is used as the gate dielectric. The method may be conducted on a remote-plasma hydrogen exposure apparatus comprising, in series, a source of a mixture of molecular and atomic hydrogen gas; a particle remover adapted to remove energetic, charged particles; a light sink; a hydrogen recombination device; and a wafer exposure chamber.
摘要翻译：用于评估用作栅极电介质的测试电介质材料的性能的装置和方法。该方法包括将电介质的涂层暴露于原子氢浓度。该方法可以包括（a）测量测试电介质中的界面态密度的初始值，（b）将涂覆的测试电介质暴露于远程等离子体中的原子氢浓度，然后（c）测量曝光后测试电介质中界面态密度的值。步骤（b）和（c）可以用逐渐增加的原子氢浓度重复，以确定作为原子氢浓度的函数的界面态密度值的变化率，其然后可能与预计的电荷 - 当电介质用作栅极电介质时，测试电介质层的击穿或击穿时间。该方法可以在远程等离子体氢曝光装置上进行，该装置包括串联的分子和原子氢气混合物的源; 适于去除高能充电颗粒的颗粒去除剂; 一个光汇氢复合装置; 和晶片曝光室。

46. 发明授权

US08772149B2 FinFET structure and method to adjust threshold voltage in a FinFET structure 有权
标题翻译： FinFET结构和调整FinFET结构中阈值电压的方法
公开(公告)号：US08772149B2
公开(公告)日：2014-07-08
申请号：US13276395
申请日：2011-10-19
申请人： Eduard A. Cartier , Brian J. Greene , Dechao Guo , Gan Wang , Yanfeng Wang , Keith Kwong Hon Wong
发明人： Eduard A. Cartier , Brian J. Greene , Dechao Guo , Gan Wang , Yanfeng Wang , Keith Kwong Hon Wong
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/785 , H01L21/02323 , H01L21/28017 , H01L27/1211 , H01L29/6656 , H01L29/66795
摘要： FinFET structures and methods of manufacturing the FinFET structures are disclosed. The method includes performing an oxygen anneal process on a gate stack of a FinFET structure to induce Vt shift. The oxygen anneal process is performed after sidewall pull down and post silicide.
摘要翻译：公开了FinFET结构和制造FinFET结构的方法。该方法包括在FinFET结构的栅极堆叠上执行氧退火处理以引起Vt偏移。氧退火工艺在侧壁下拉和硅化后进行。

47. 发明授权

US08716807B2 Fabrication of devices having different interfacial oxide thickness via lateral oxidation 有权
标题翻译：通过侧面氧化制备具有不同界面氧化物厚度的器件
公开(公告)号：US08716807B2
公开(公告)日：2014-05-06
申请号：US13571521
申请日：2012-08-10
申请人： Jin Cai , Eduard A. Cartier , Martin M. Frank , Marwan H. Khater
发明人： Jin Cai , Eduard A. Cartier , Martin M. Frank , Marwan H. Khater
IPC分类号： H01L21/70
CPC分类号： H01L21/823468 , H01L21/28176 , H01L21/28247 , H01L21/823462 , H01L21/823857 , H01L21/823864 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/78
摘要： A semiconductor device includes a first field effect transistor (FET) and a second FET located on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer, wherein the second interfacial oxide layer of the second FET is thicker than the first interfacial oxide layer of the first FET; and a recess located in the substrate adjacent to the second FET.
摘要翻译：半导体器件包括位于衬底上的第一场效应晶体管（FET）和第二FET，所述第一FET包括第一界面氧化物层，所述第二FET包括第二界面氧化物层，其中所述第二界面氧化物层第二FET比第一FET的第一界面氧化物层厚; 以及位于与第二FET相邻的衬底中的凹部。

48. 发明授权

US08716118B2 Replacement gate structure for transistor with a high-K gate stack 失效
标题翻译：具有高K栅极堆叠的晶体管的替代栅极结构
公开(公告)号：US08716118B2
公开(公告)日：2014-05-06
申请号：US13345295
申请日：2012-01-06
申请人： Takashi Ando , Eduard A. Cartier , Unoh Kwon , Vijay Narayanan
发明人： Takashi Ando , Eduard A. Cartier , Unoh Kwon , Vijay Narayanan
IPC分类号： H01L21/3205
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/28185 , H01L27/1203 , H01L29/4908 , H01L29/4966 , H01L29/51 , H01L29/518 , H01L29/66545
摘要： A transistor includes a semiconductor layer and a gate structure located on the semiconductor layer. The gate structure includes a first dielectric layer. The first dielectric layer includes a doped region and an undoped region below the doped region. A second dielectric layer is located on the first dielectric layer, and a first metal nitride layer is located on the second dielectric layer. The doped region of the first dielectric layer comprises dopants from the second dielectric layer. Source and drain regions in the semiconductor layer are located on opposite sides of the gate structure.
摘要翻译：晶体管包括位于半导体层上的半导体层和栅极结构。栅极结构包括第一介电层。第一介电层包括掺杂区域和掺杂区域下面的未掺杂区域。第二电介质层位于第一电介质层上，第一金属氮化物层位于第二电介质层上。第一介电层的掺杂区域包括来自第二介电层的掺杂剂。半导体层中的源极和漏极区位于栅极结构的相对侧上。

49. 发明授权

US08035173B2 CMOS transistors with differential oxygen content high-K dielectrics 有权
标题翻译：具有差异氧含量高K电介质的CMOS晶体管
公开(公告)号：US08035173B2
公开(公告)日：2011-10-11
申请号：US12712371
申请日：2010-02-25
申请人： Huiming Bu , Eduard A. Cartier , Bruce B. Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
发明人： Huiming Bu , Eduard A. Cartier , Bruce B. Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
IPC分类号： H01L29/78
CPC分类号： H01L21/823864 , H01L21/823814 , H01L21/823857 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/4908 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.
摘要翻译：在半导体衬底上形成包含第一高k电介质部分的NFET和包含第二高k栅极电介质部分的PFET。栅极侧壁氮化物形成在NFET的栅极上，而PFET的侧壁保持没有栅极侧壁氮化物。直接在PFET栅极堆叠的侧壁上和NFET上的栅极侧壁氮化物上形成氧化物间隔物。在高温处理之后，第一和第二介质部分含有非化学计量的缺氧高k电介质材料。半导体结构在氧气环境中进行退火，在该环境中，氧气通过氧化物间隔物扩散到第二高k电介质部分。 PFET包括更高化学计量的高k电介质材料，并且NFET包含较少化学计量的高k电介质材料。本发明优化了PFET和NFET的阈值电压。

50. 发明授权

US07999323B2 Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices 有权
标题翻译：使用金属/金属氮化物双层作为自对准积极缩放的CMOS器件中的栅电极
公开(公告)号：US07999323B2
公开(公告)日：2011-08-16
申请号：US12542087
申请日：2009-08-17
申请人： Eduard A. Cartier , Matthew W. Copel , Bruce B. Doris , Rajarao Jammy , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri , Keith Kwong Hon Wong
发明人： Eduard A. Cartier , Matthew W. Copel , Bruce B. Doris , Rajarao Jammy , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri , Keith Kwong Hon Wong
IPC分类号： H01L29/00
CPC分类号： H01L21/823842
摘要： The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.
摘要翻译：本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。根据本发明，所述至少一个nMOS器件包括栅极堆叠，其包括栅极电介质，功函数小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。本发明还提供了制造这种CMOS结构的方法。

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