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41. 发明授权

US07784003B2 Estimation of process variation impact of slack in multi-corner path-based static timing analysis 失效
标题翻译：基于多角路径静态时序分析的松弛过程变化影响的估计
公开(公告)号：US07784003B2
公开(公告)日：2010-08-24
申请号：US11679171
申请日：2007-02-26
申请人： Nathan C. Buck , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Kerim Kalafala , Jeffrey M. Ritzinger , Xiaoyue Wang
发明人： Nathan C. Buck , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Kerim Kalafala , Jeffrey M. Ritzinger , Xiaoyue Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and system for reducing a number of paths to be analyzed in a multi-corner static timing analysis. An estimated upper slack variation based on a non-common path delay for a racing path is utilized in determining if a multi-corner static timing analysis may be bypassed for a racing path. In another example, an estimated maximum RSS credit based on a total delay for a racing path is utilized in determining if a multi-corner static timing analysis may be bypassed for a racing path.
摘要翻译：一种用于在多角静态时序分析中减少要分析的路径的数量的方法和系统。基于用于赛车路径的非公共路径延迟的估计的上部松弛变化被用于确定是否可以绕过赛车路径绕过多角度静态时序分析。在另一示例中，基于用于赛车路径的总延迟的估计的最大RSS信用被用于确定是否可以为赛车路径绕过多角度静态时序分析。

42. 发明授权

US07750648B2 Method to quickly estimate inductance for timing models 有权
标题翻译：快速估计定时模型电感的方法
公开(公告)号：US07750648B2
公开(公告)日：2010-07-06
申请号：US12059275
申请日：2008-03-31
申请人： Eric A. Foreman , Peter A. Habitz , Mark R. Lasher , William J. Livingstone , Gregory M. Schaeffer
发明人： Eric A. Foreman , Peter A. Habitz , Mark R. Lasher , William J. Livingstone , Gregory M. Schaeffer
IPC分类号： G01R27/00
CPC分类号： G01R27/2611 , G01R27/28 , G06F17/5036 , G06F2217/84
摘要： A method of estimating an inductance delay includes determining a resistance-capacitance (RC) delay with resistances and capacitances of a network and estimating an inductance delay of the network by determining a propagation delay of an electromagnetic (EM) field across wires of the network. Additionally, the method includes determining if the RC delay is below a specified threshold and adding the estimated inductance delay to the RC delay to determine a total time to propagate voltage swings through the network if the RC delay is below the specified threshold.
摘要翻译：估计电感延迟的方法包括通过确定网络的电线（EM）场的传播延迟来确定网络的电阻和电容的电阻 - 电容（RC）延迟并估计网络的电感延迟。此外，该方法包括确定RC延迟是否低于指定的阈值，并将估计的电感延迟与RC延迟相加，以确定如果RC延迟低于指定阈值，则传播通过网络的电压摆幅的总时间。

43. 发明申请

US20090243630A1 METHOD TO QUICKLY ESTIMATE INDUCTANCE FOR TIMING MODELS 有权
标题翻译：快速估计时序模型电感的方法
公开(公告)号：US20090243630A1
公开(公告)日：2009-10-01
申请号：US12059275
申请日：2008-03-31
申请人： Eric A. Foreman , Peter A. Habitz , Mark R. Lasher , William J. Livingstone , Gregory M. Schaeffer
发明人： Eric A. Foreman , Peter A. Habitz , Mark R. Lasher , William J. Livingstone , Gregory M. Schaeffer
IPC分类号： G01R27/28
CPC分类号： G01R27/2611 , G01R27/28 , G06F17/5036 , G06F2217/84
摘要： A method of estimating an inductance delay includes determining a resistance-capacitance (RC) delay with resistances and capacitances of a network and estimating an inductance delay of the network by determining a propagation delay of an electromagnetic (EM) field across wires of the network. Additionally, the method includes determining if the RC delay is below a specified threshold and adding the estimated inductance delay to the RC delay to determine a total time to propagate voltage swings through the network if the RC delay is below the specified threshold.
摘要翻译：估计电感延迟的方法包括通过确定网络的电线（EM）场的传播延迟来确定网络的电阻和电容的电阻 - 电容（RC）延迟并估计网络的电感延迟。此外，该方法包括确定RC延迟是否低于指定的阈值，并将估计的电感延迟与RC延迟相加，以确定如果RC延迟低于指定阈值，则传播通过网络的电压摆幅的总时间。

44. 发明授权

US07401307B2 Slack sensitivity to parameter variation based timing analysis 有权
标题翻译：对基于参数变化的时序分析的松弛敏感性
公开(公告)号：US07401307B2
公开(公告)日：2008-07-15
申请号：US10904309
申请日：2004-11-03
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
摘要翻译：公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。对于每个独立参数重复此步骤。然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。然后将失败的定时终点根据其故障系数进行优先级修改。所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。

45. 发明授权

US08656207B2 Method for modeling variation in a feedback loop of a phase-locked loop 失效
标题翻译：用于建模锁相环反馈环路变化的方法
公开(公告)号：US08656207B2
公开(公告)日：2014-02-18
申请号：US12638060
申请日：2009-12-15
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz
IPC分类号： G06F1/00 , G06F1/04 , G06F1/24 , G06F11/00 , H03L7/06
CPC分类号： H03L7/08
摘要： A method performs statistical static timing analysis of a network that includes a phase-locked loop and a feedback path. The feedback path comprises a set of delays operatively connected from the output of the phase-locked loop back to the input of the phase-locked loop. One embodiment herein computes a statistical feedback path delay for the feedback path. The method can use a separate statistical parameter to represent random uncorrelated delay variation for each delay in the feedback path. The method also computes an output arrival time for the phase-locked loop based on the negative of the statistical feedback path delay.
摘要翻译：一种方法执行包括锁相环和反馈路径的网络的统计静态时序分析。反馈路径包括从锁相环的输出到锁相环的输入可操作地连接的一组延迟。这里的一个实施例计算反馈路径的统计反馈路径延迟。该方法可以使用单独的统计参数来表示反馈路径中的每个延迟的随机不相关的延迟变化。该方法还基于统计反馈路径延迟的负值计算锁相环的输出到达时间。

46. 发明申请

US20110126163A1 METHOD TO REDUCE DELAY VARIATION BY SENSITIVITY CANCELLATION 失效
标题翻译：通过灵敏度消除来减少延迟变化的方法
公开(公告)号：US20110126163A1
公开(公告)日：2011-05-26
申请号：US12625139
申请日：2009-11-24
申请人： Peter A. Habitz , Eric A. Foreman , Gustavo E. Tellez
发明人： Peter A. Habitz , Eric A. Foreman , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/12 , G06F2217/84 , Y02P90/265
摘要： A method receives an initial circuit design. The circuit design includes at least one path having at least one beginning point comprising a source, at least one ending point comprising a sink, and one or more circuit elements between the source and the sink. The method evaluates timing performance parameter sensitivities to manufacturing variations of each of the elements to identify how much each element will increase or decrease the timing performance parameter of the path for each change in each manufacturing variable associated with manufacturing the elements. Further, the method alters the elements within the path until elements that produce positive changes to the timing performance parameter for a given manufacturing variable change approximately equals (in magnitude) elements that produce negative changes to the timing performance parameter for the given manufacturing variable change, to produce an altered circuit design.
摘要翻译：一种方法接收初始电路设计。该电路设计包括至少一个路径，该至少一个路径具有包括源的至少一个起始点，包括宿的至少一个终点以及源和宿之间的一个或多个电路元件。该方法评估每个元件的制造变化的时序性能参数灵敏度，以识别每个元件将增加或减少与制造元件相关联的每个制造变量中的每个变化的路径的时序性能参数。此外，该方法改变路径内的元素，直到产生对于给定制造变量的定时性能参数的正变化的元素大致等于（在大小上）元素，该元素对于给定的制造变量变化而对定时性能参数产生负变化，以产生改变的电路设计。

47. 发明申请

US20100318951A1 SYSTEM AND METHOD FOR DEVICE HISTORY BASED DELAY VARIATION ADJUSTMENT DURING STATIC TIMING ANALYSIS 有权
标题翻译：基于静态时序分析的基于设备历史的延迟变化调整系统与方法
公开(公告)号：US20100318951A1
公开(公告)日：2010-12-16
申请号：US12484293
申请日：2009-06-15
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources of variability of history based components of delay variability, and a relationship between the sources of variability and one or more bounded device histories. Then, inputting history bounds for at least one signal of the integrated circuit design, and computing and propagating history bounds through at least one first segment of the integrated circuit design to at least one signal of the integrated circuit design. Further, the method may include evaluating from at least one of the propagated history bounds, device history bounds for at least one second segment of the integrated circuit design, and based on the evaluated device history bounds, adjusting at least one of a value of the history based delay variability and propagation of timing.
摘要翻译：一种用于在集成电路设计的静态时序分析期间调整基于历史的延迟变化的系统和方法。该方法可以包括通过延迟变异性的基于历史的组件的变异源获得信息，以及变异源与一个或多个有界设备历史之间的关系。然后，为集成电路设计的至少一个信号输入历史界限，并且通过集成电路设计的至少一个第一段将集成电路设计的至少一个信号计算和传播历史界限。此外，该方法可以包括从至少一个传播的历史界限评估集成电路设计的至少一个第二段的设备历史界限，以及基于所评估的设备历史界限，调整至少一个基于历史的延迟变异性和时间传播。

48. 发明申请

US20110140745A1 Method for Modeling Variation in a Feedback Loop of a Phase-Locked Loop 失效
标题翻译：用于建模锁相环路反馈环路变化的方法
公开(公告)号：US20110140745A1
公开(公告)日：2011-06-16
申请号：US12638060
申请日：2009-12-15
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz
IPC分类号： H03L7/06
CPC分类号： H03L7/08
摘要： A method performs statistical static timing analysis of a network that includes a phase-locked loop and a feedback path. The feedback path comprises a set of delays operatively connected from the output of the phase-locked loop back to the input of the phase-locked loop. One embodiment herein computes a statistical feedback path delay for the feedback path. The method can use a separate statistical parameter to represent random uncorrelated delay variation for each delay in the feedback path. The method also computes an output arrival time for the phase-locked loop based on the negative of the statistical feedback path delay.
摘要翻译：一种方法执行包括锁相环和反馈路径的网络的统计静态时序分析。反馈路径包括从锁相环的输出到锁相环的输入可操作地连接的一组延迟。这里的一个实施例计算反馈路径的统计反馈路径延迟。该方法可以使用单独的统计参数来表示反馈路径中的每个延迟的随机不相关的延迟变化。该方法还基于统计反馈路径延迟的负值计算锁相环的输出到达时间。

49. 发明授权

US07962874B2 Method and system for evaluating timing in an integrated circuit 有权
标题翻译：用于评估集成电路中的定时的方法和系统
公开(公告)号：US07962874B2
公开(公告)日：2011-06-14
申请号：US12183549
申请日：2008-07-31
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G01R31/3016
摘要： Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.
摘要翻译：用于分析集成电路中的定时并减少静态时序分析（STA）中定时松弛计算中的悲观情况的方法。该方法涉及分组和消除在早期和晚期电路路径中具有类似延迟的元件的延迟贡献。使用具有不同延迟的元件的延迟贡献来计算调整的定时松弛。在一些实施例中，具有不同延迟的元件的延迟贡献是根和平方。本发明的实施例提供了用于减少由于基于单元和线依赖的延迟引起的悲观的方法。在本发明的实施例中考虑的延迟可以包括由于路径中的元件的位置而导致的延迟。

50. 发明申请

US20110035714A1 SYSTEM AND METHOD FOR COMMON HISTORY PESSIMISM RELIEF DURING STATIC TIMING ANALYSIS 有权
标题翻译：系统和方法在静态时序分析期间的共同历史缓解
公开(公告)号：US20110035714A1
公开(公告)日：2011-02-10
申请号：US12538229
申请日：2009-08-10
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A system and method for adjustment of modeled timing data variation as a function of past state and/or switching history during static timing analysis. One illustrative embodiment may include inputting and asserting at least one of initial signal history bound and explicit device history bound constraints for at least one signal of a circuit design and evaluating for a segment processed during a forward propagation of block based static timing analysis whether any input signal to a current segment has a bounded history, at least one of propagated and asserted. The method may further include evaluating for the segment whether history bounds are downstream from a gating restriction, and processing a next segment until there are no further segments.
摘要翻译：一种用于在静态时序分析期间调整作为过去状态和/或切换历史的函数的建模定时数据变化的系统和方法。一个说明性实施例可以包括输入和断言用于电路设计的至少一个信号的初始信号历史约束和显式设备历史约束约束中的至少一个，并且针对在基于块的静态时序分析的正向传播期间处理的段来评估是否有任何输入对当前段的信号具有有界历史，至少一个传播和断言。该方法可以进一步包括评估该段是否历史边界是在门控限制的下游，以及处理下一个段，直到没有进一步的段。

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