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41. 发明授权

US07498271B1 Nitrogen based plasma process for metal gate MOS device 有权
标题翻译：金属栅MOS器件的氮基等离子体工艺
公开(公告)号：US07498271B1
公开(公告)日：2009-03-03
申请号：US12145035
申请日：2008-06-24
申请人： Ricardo A. Donaton , Rashmi Jha , Siddarth A. Krishnan , Xi Li , Renee T. Mo , Naim Moumen , Wesley C. Natzle , Ravikumar Ramachandran , Richard S. Wise
发明人： Ricardo A. Donaton , Rashmi Jha , Siddarth A. Krishnan , Xi Li , Renee T. Mo , Naim Moumen , Wesley C. Natzle , Ravikumar Ramachandran , Richard S. Wise
IPC分类号： H01L21/31
CPC分类号： H01L21/31138 , H01L21/28202 , H01L21/31155 , H01L21/823828 , H01L21/823878 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention, in one embodiment, provides a method of forming a gate structure including providing a substrate including a semiconducting device region, a high-k dielectric material present atop the semiconducting device region, and a metal gate conductor atop the high-k dielectric material, applying a photoresist layer atop the metal gate conductor; patterning the photoresist layer to provide an etch mask overlying a portion of the metal gate conductor corresponding to a gate stack; etching the metal gate conductor and the high-k dielectric material selective to the etch mask; and removing the etch mask with a substantially oxygen free nitrogen based plasma.
摘要翻译：本发明在一个实施例中提供了一种形成栅极结构的方法，该栅极结构包括提供包括半导体器件区域的衬底，在半导体器件区域顶部存在的高k电介质材料以及高k电介质顶部的金属栅极导体材料，在金属栅极导体顶上施加光致抗蚀剂层; 图案化光致抗蚀剂层以提供覆盖对应于栅极堆叠的金属栅极导体的一部分的蚀刻掩模; 蚀刻对蚀刻掩模有选择性的金属栅极导体和高k电介质材料; 并用基本上不含氧的氮气等离子体去除蚀刻掩模。

42. 发明授权

US06355567B1 Retrograde openings in thin films 失效
标题翻译：薄膜逆行开口
公开(公告)号：US06355567B1
公开(公告)日：2002-03-12
申请号：US09345646
申请日：1999-06-30
申请人： Scott D. Halle , Paul C. Jamison , David E. Kotecki , Richard S. Wise
发明人： Scott D. Halle , Paul C. Jamison , David E. Kotecki , Richard S. Wise
IPC分类号： H01L21311
CPC分类号： H01L21/76879 , H01L21/31116 , H01L21/76804 , H01L21/7682 , H01L21/76885
摘要： Retrograde openings in thin films and the process for forming the same. The openings may include conductive materials formed within the openings to serve as a wiring pattern which includes wires having tapered cross sections. The process involves a two-step etching procedure for forming a retrograde opening within a film having a gradient of a characteristic that influences the etch rate for a chosen etchant species. An opening is first formed within the film by an anisotropic etch process. The opening is then converted to an opening including retrograde features by an isotropic etch process which is selective to the characteristic. Thereafter, the retrograde opening is filled with a conductive material, in one case, by electroplating or other deposition techniques.
摘要翻译：薄膜中的逆行开口及其形成方法。开口可以包括形成在开口内的导电材料，以用作包括具有锥形横截面的导线的布线图案。该方法涉及用于在膜内形成具有影响所选择的蚀刻剂物质的蚀刻速率的特性梯度的逆向开口的两步蚀刻方法。首先通过各向异性蚀刻工艺在膜内形成开口。然后通过对特性有选择性的各向同性蚀刻工艺将开口转换成包括逆行特征的开口。此后，逆行开口填充有导电材料，在一种情况下，通过电镀或其它沉积技术。

43. 发明授权

US08435891B2 Converting metal mask to metal-oxide etch stop layer and related semiconductor structure 有权
标题翻译：将金属掩模转换为金属氧化物蚀刻停止层和相关的半导体结构
公开(公告)号：US08435891B2
公开(公告)日：2013-05-07
申请号：US13151646
申请日：2011-06-02
申请人： Brett H. Engel , Ying Li , Viraj Y. Sardesai , Richard S. Wise
发明人： Brett H. Engel , Ying Li , Viraj Y. Sardesai , Richard S. Wise
IPC分类号： H01L21/283
CPC分类号： H01L21/31144 , H01L21/02178 , H01L21/02244 , H01L21/02252 , H01L21/76804 , H01L21/7681 , H01L21/76829
摘要： A method includes providing a semiconductor structure including a plurality of devices; depositing a nitride cap over the semiconductor structure; forming an aluminum mask over the nitride cap, the aluminum mask including a plurality of first openings; converting the aluminum mask to an aluminum oxide etch stop layer; and performing middle-of-line fabrication processing, leaving the aluminum oxide etch stop layer in place. A semiconductor structure includes a plurality of devices on a substrate; a nitride cap over the plurality of devices; an aluminum oxide etch stop layer over the nitride cap; an inter-level dielectric (ILD) over the aluminum oxide etch stop layer; and a plurality of contacts extending through the ILD, the aluminum oxide etch stop layer and the nitride cap to the plurality of devices.
摘要翻译：一种方法包括提供包括多个装置的半导体结构; 在所述半导体结构上沉积氮化物盖; 在所述氮化物盖上形成铝掩模，所述铝掩模包括多个第一开口; 将铝掩模转变成氧化铝蚀刻停止层; 并执行中间线制造处理，将氧化铝蚀刻停止层留在原位。半导体结构在基板上包括多个器件; 多个装置上的氮化物盖; 在氮化物盖上方的氧化铝蚀刻停止层; 氧化铝蚀刻停止层上的层间电介质（ILD）; 以及穿过ILD延伸的多个触点，氧化铝蚀刻停止层和氮化物帽到多个器件。

44. 发明申请

US20120288687A1 EDGE PROTECTION SEAL FOR BONDED SUBSTRATES 有权
标题翻译：贴边基板的边缘保护密封
公开(公告)号：US20120288687A1
公开(公告)日：2012-11-15
申请号：US13556369
申请日：2012-07-24
申请人： Mukta G. Farooq , Emily Kinser , Richard S. Wise , Hakeem B.S. Akinmade-Yusuff
发明人： Mukta G. Farooq , Emily Kinser , Richard S. Wise , Hakeem B.S. Akinmade-Yusuff
IPC分类号： B32B3/02 , B29C65/48
CPC分类号： H01L21/02263 , H01L21/187 , H01L21/76898 , H01L25/074 , H01L25/50 , H01L2924/0002 , H01L2924/00
摘要： A dielectric material layer is deposited on exposed surfaces of a bonded structure that includes a first substrate and a second substrate. The dielectric material layer is formed on an exposed planar surface of a second substrate and the entirety of peripheral sidewalls of the first and second substrates. The dielectric material layer can be formed by chemical vapor deposition, atomic layer deposition, or plasma induced deposition. Further, the dielectric material layer seals the entire periphery of the interface between the first and second substrates. If a planar portion of the dielectric material layer can be removed by planarization to facilitate thinning of the bonded structure, the remaining portion of the dielectric material layer can form a dielectric ring.
摘要翻译：介电材料层沉积在包括第一基板和第二基板的接合结构的暴露表面上。介电材料层形成在第二基板的暴露的平坦表面和第一和第二基板的整个周边侧壁上。介电材料层可以通过化学气相沉积，原子层沉积或等离子体诱导沉积形成。此外，介电材料层密封第一和第二基板之间的界面的整个周边。如果可以通过平坦化去除电介质材料层的平面部分以便于键合结构的薄化，则介电材料层的剩余部分可以形成介电环。

45. 发明授权

US08287980B2 Edge protection seal for bonded substrates 失效
标题翻译：粘合基材的边缘保护密封
公开(公告)号：US08287980B2
公开(公告)日：2012-10-16
申请号：US12608363
申请日：2009-10-29
申请人： Mukta G. Farooq , Emily Kinser , Richard S. Wise , Hakeem B. S. Akinmade-Yusuff
发明人： Mukta G. Farooq , Emily Kinser , Richard S. Wise , Hakeem B. S. Akinmade-Yusuff
IPC分类号： B32B1/04 , B32B38/00
CPC分类号： H01L21/02263 , H01L21/187 , H01L21/76898 , H01L25/074 , H01L25/50 , H01L2924/0002 , H01L2924/00
摘要： A dielectric material layer is deposited on exposed surfaces of a bonded structure that includes a first substrate and a second substrate. The dielectric material layer is formed on an exposed planar surface of a second substrate and the entirety of peripheral sidewalls of the first and second substrates. The dielectric material layer can be formed by chemical vapor deposition, atomic layer deposition, or plasma induced deposition. Further, the dielectric material layer seals the entire periphery of the interface between the first and second substrates. If a planar portion of the dielectric material layer can be removed by planarization to facilitate thinning of the bonded structure, the remaining portion of the dielectric material layer can form a dielectric ring.
摘要翻译：介电材料层沉积在包括第一基板和第二基板的接合结构的暴露表面上。介电材料层形成在第二基板的暴露的平坦表面和第一和第二基板的整个周边侧壁上。介电材料层可以通过化学气相沉积，原子层沉积或等离子体诱导沉积形成。此外，介电材料层密封第一和第二基板之间的界面的整个周边。如果可以通过平坦化去除电介质材料层的平面部分以便于键合结构的薄化，则介电材料层的剩余部分可以形成介电环。

46. 发明授权

US08030157B1 Liner protection in deep trench etching 失效
标题翻译：衬里保护深沟蚀刻
公开(公告)号：US08030157B1
公开(公告)日：2011-10-04
申请号：US12782050
申请日：2010-05-18
申请人： Habib Hichri , Ahmad D. Katnani , Kaushik A. Kumar , Narender Rana , Richard S. Wise , Hakeem B. S. Akinmade-Yusuff
发明人： Habib Hichri , Ahmad D. Katnani , Kaushik A. Kumar , Narender Rana , Richard S. Wise , Hakeem B. S. Akinmade-Yusuff
IPC分类号： H01L21/8242
CPC分类号： H01L21/76232
摘要： A method of forming a trench in a semiconductor device formed of a substrate and a first layer formed over the substrate includes forming an initial trench that passes through the first layer to the substrate, the initial trench having a diameter that decreases from a first diameter to a second diameter, the second diameter being measured at a distance closer to the substrate than the first diameter; exposing the trench to a dopant via an orthogonal ion implant to form doped regions sidewalls of the trench; and etching the trench to remove at least some of the doped regions.
摘要翻译：在由衬底和形成在衬底上的第一层形成的半导体器件中形成沟槽的方法包括形成通过第一层到衬底的初始沟槽，初始沟槽的直径从第一直径减小到第二直径，第二直径在比第一直径更靠近基板的距离处被测量; 通过正交离子注入将沟槽暴露于掺杂剂以形成沟槽的掺杂区域侧壁; 并蚀刻沟槽以去除至少一些掺杂区域。

47. 发明申请

US20110180880A1 DUAL METAL AND DUAL DIELECTRIC INTEGRATION FOR METAL HIGH-K FETS 有权
标题翻译：金属高K FET的双金属和双介电一体化
公开(公告)号：US20110180880A1
公开(公告)日：2011-07-28
申请号：US13080962
申请日：2011-04-06
申请人： Michael P. Chudzik , Wiliam K. Henson , Rashmi Jha , Yue Liang , Ravikumar Ramachandran , Richard S. Wise
发明人： Michael P. Chudzik , Wiliam K. Henson , Rashmi Jha , Yue Liang , Ravikumar Ramachandran , Richard S. Wise
IPC分类号： H01L27/092
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/823842 , H01L21/823857 , H01L29/49 , H01L29/7833
摘要： The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.
摘要翻译：在一个实施例中，本发明提供一种形成半导体器件的方法，该半导体器件包括提供包括第一导电类型区域和第二导电类型区域的衬底; 在所述基板的第一导电类型区域和所述第二导电类型区域之上形成包括栅极电介质的栅极堆叠和覆盖所述高k栅极电介质的第一金属栅极导体; 去除存在于第一导电类型区域中的第一金属栅极导体的一部分以暴露存在于第一导电类型区域中的栅极电介质; 将氮基等离子体施加到所述基板，其中所述氮基等离子体氮化存在于所述第一导电类型区域中的所述栅极电介质，并且氮化所述第二导电类型区域中存在的所述第一金属栅极导体; 以及形成覆盖存在于第一导电类型区域中的至少栅极电介质的第二金属栅极导体。

48. 发明授权

US07859013B2 Metal oxide field effect transistor with a sharp halo 有权
标题翻译：金属氧化物场效应晶体管具有尖锐的光晕
公开(公告)号：US07859013B2
公开(公告)日：2010-12-28
申请号：US11955591
申请日：2007-12-13
申请人： Huajie Chen , Judson R. Holt , Rangarajan Jagannathan , Wesley C. Natzle , Michael R. Sievers , Richard S. Wise
发明人： Huajie Chen , Judson R. Holt , Rangarajan Jagannathan , Wesley C. Natzle , Michael R. Sievers , Richard S. Wise
IPC分类号： H01L21/02
CPC分类号： H01L29/66636 , H01L29/6659 , H01L29/7833
摘要： Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.
摘要翻译：公开了具有限定的限定的卤素的MOSFET的实施例，其限定的源极/漏极扩展部分以及形成MOSFET的方法。蚀刻半导体层以形成切割栅极介电层的凹部。低能量植入物形成晕轮。然后，执行COR预清洁，并且通过外延沉积填充凹部。外延可以被原位掺杂或随后植入以形成源/漏扩展。或者，蚀刻之后紧接着是COR预清洁，随后进行外延沉积以填充凹部。在外延沉积工艺期间，沉积的材料被掺杂以形成原位掺杂的光晕，然后切换掺杂剂以形成邻近光晕的原位掺杂的源极/漏极延伸。或者，在形成原位掺杂的光晕之后，进行沉积工艺而没有掺杂剂，并且使用注入来形成源极/漏极延伸部。

49. 发明申请

US20100258881A1 DUAL METAL AND DUAL DIELECTRIC INTEGRATION FOR METAL HIGH-K FETS 有权
标题翻译：金属高K FET的双金属和双介电一体化
公开(公告)号：US20100258881A1
公开(公告)日：2010-10-14
申请号：US12423236
申请日：2009-04-14
申请人： Michael P. Chudzik , Wiliam K. Henson , Rashmi Jha , Yue Liang , Ravikumar Ramachandran , Richard S. Wise
发明人： Michael P. Chudzik , Wiliam K. Henson , Rashmi Jha , Yue Liang , Ravikumar Ramachandran , Richard S. Wise
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/823842 , H01L21/823857 , H01L29/49 , H01L29/7833
摘要： The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.
摘要翻译：在一个实施例中，本发明提供一种形成半导体器件的方法，该半导体器件包括提供包括第一导电类型区域和第二导电类型区域的衬底; 在所述基板的第一导电类型区域和所述第二导电类型区域之上形成包括栅极电介质的栅极堆叠和覆盖所述高k栅极电介质的第一金属栅极导体; 去除存在于第一导电类型区域中的第一金属栅极导体的一部分以暴露存在于第一导电类型区域中的栅极电介质; 将氮基等离子体施加到所述基板，其中所述氮基等离子体氮化存在于所述第一导电类型区域中的所述栅极电介质，并且氮化所述第二导电类型区域中存在的所述第一金属栅极导体; 以及形成覆盖存在于第一导电类型区域中的至少栅极电介质的第二金属栅极导体。

50. 发明授权

US06686296B1 Nitrogen-based highly polymerizing plasma process for etching of organic materials in semiconductor manufacturing 失效
标题翻译：用于半导体制造中有机材料蚀刻的氮基高聚合等离子体工艺
公开(公告)号：US06686296B1
公开(公告)日：2004-02-03
申请号：US09723529
申请日：2000-11-28
申请人： Gregory Costrini , Peter D. Hoh , Richard S. Wise , Wendy Yan
发明人： Gregory Costrini , Peter D. Hoh , Richard S. Wise , Wendy Yan
IPC分类号： H01L213065
CPC分类号： H01L21/31138 , H01L21/0276
摘要： A method of etching an organic antireflective film layer underlying a patterned resist layer on a semiconductor substrate by contacting the exposed organic film with a fluorocarbon and nitrogen etchant in the presence of a plasma-generated energy and removing exposed areas of the organic film with the etchant. An oxide layer underlying the organic film layer is substantially undamaged after contact with the etchant. The plasma is a high density plasma and preferably contains argon, C4F8, and nitrogen.
摘要翻译：一种通过在等离子体产生的能量存在下使暴露的有机膜与碳氟化合物和氮气蚀刻剂接触来蚀刻半导体衬底下的图案化抗蚀剂层下面的有机抗反射膜层的方法，并用蚀刻剂去除有机膜的暴露区域。在与蚀刻剂接触之后，有机薄膜层下面的氧化物层基本上没有损坏。等离子体是高密度等离子体，优选含有氩，C 4 F 8和氮。

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