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41. 发明授权

US5898859A Address shadow feature and methods of using the same 失效
标题翻译：地址阴影功能和使用方法
公开(公告)号：US5898859A
公开(公告)日：1999-04-27
申请号：US724369
申请日：1996-10-01
申请人： James P. Kardach , Tuong Trieu
发明人： James P. Kardach , Tuong Trieu
IPC分类号： G06F15/16
CPC分类号： G06F13/24
摘要： An address shadow feature and methods of using the same. A slave controller of the present invention includes an address register coupled to receive a device address from a secondary bus interface. A match circuit is coupled to the address register and compares the device address to a shadow address, generating a match signal upon detection of a match between the shadow address and the device address. An interrupt generation circuit generates an interrupt signal in response to the match signal.
摘要翻译：地址阴影特征及使用方法。本发明的从属控制器包括地址寄存器，其耦合以从次级总线接口接收设备地址。匹配电路耦合到地址寄存器，并将器件地址与阴影地址进行比较，在检测到阴影地址和器件地址之间的匹配时产生匹配信号。中断产生电路响应于匹配信号产生中断信号。

42. 发明授权

US5889964A Method and apparatus for docking and undocking a notebook computer to and from a docking station while the notebook computer is in an active state 失效
标题翻译：当笔记本计算机处于活动状态时，用于将笔记本计算机与对接站对准和脱离坞的方法和装置
公开(公告)号：US5889964A
公开(公告)日：1999-03-30
申请号：US754399
申请日：1996-11-21
申请人： Sung-Soo Cho , Feng Deng , Pranav S. Shah , Diane Bryant , James P. Kardach
发明人： Sung-Soo Cho , Feng Deng , Pranav S. Shah , Diane Bryant , James P. Kardach
IPC分类号： G06F1/16 , G06F13/40 , G06F13/00
CPC分类号： G06F1/1632 , G06F13/4081 , Y02B60/1228 , Y02B60/1235
摘要： Prior art quiet docking and undocking methods used an interface that was located within the notebook computer, thus adding to the complexity, weight, and power consumption of the notebook computer. The present invention provides for a method for quiet docking and undocking of a notebook computer using interface circuitry located within the docking station. Moreover, the method of the present invention provides for docking and undocking whether the notebook computer is in a powered-on or suspend mode. The notebook computer is docked and undocked to the docking station such that any transaction occurring on the system bus during the docking/undocking sequence is not affected.
摘要翻译：现有技术的安静对接和脱离方法使用位于笔记本计算机内的接口，从而增加了笔记本计算机的复杂性，重量和功率消耗。本发明提供一种用于使用位于对接站内的接口电路来使笔记本计算机安静地对接和脱离连接的方法。此外，本发明的方法提供对接和脱离笔记本计算机是否处于通电或挂起模式。笔记本电脑停靠在对接站上，使得在对接/取消连接顺序期间在系统总线上发生的任何事务都不受影响。

43. 发明授权

US5884088A System, apparatus and method for managing power in a computer system 失效
标题翻译：用于在计算机系统中管理电力的系统，装置和方法
公开(公告)号：US5884088A
公开(公告)日：1999-03-16
申请号：US893443
申请日：1997-07-10
申请人： James P. Kardach , Chih-Hung Chung , Jason Ziller
发明人： James P. Kardach , Chih-Hung Chung , Jason Ziller
IPC分类号： G06F1/32
CPC分类号： G06F1/3215 , G06F1/3237 , G06F1/3275 , Y02B60/1221 , Y02B60/1228
摘要： A computer system is provided for monitoring the activity of a bus controller of a processor and responsive thereto for controlling the power consumption of a target controller such as a memory controller coupled to the bus controller. The computer system includes a bus, a processor having a bus controller coupled to the bus, and a bus activity monitor, coupled to the bus controller, generating a bus activity signal indicative of activity in the bus controller. The computer system also includes a target controller, coupled to the bus controller, for controlling the exchange of information between the processor and a target circuit. The target controller has an input for receiving a sequencing signal. The computer system additionally includes a power management circuit for controlling a power consumption of the target controller. The power management circuit has an input for receiving the bus activity signal and, an output for generating the sequencing signal in response to the bus activity signal.
摘要翻译：提供了一种用于监视处理器的总线控制器的活动并响应于此来控制诸如连接到总线控制器的存储器控制器的目标控制器的功耗的计算机系统。计算机系统包括总线，具有耦合到总线的总线控制器的处理器和耦合到总线控制器的总线活动监视器，生成指示总线控制器中的活动的总线活动信号。计算机系统还包括耦合到总线控制器的目标控制器，用于控制处理器与目标电路之间的信息交换。目标控制器具有用于接收排序信号的输入。计算机系统还包括用于控制目标控制器的功耗的电源管理电路。功率管理电路具有用于接收总线活动信号的输入端和用于响应于总线活动信号产生排序信号的输出。

44. 发明授权

US5862389A Method and apparatus for selectively invoking a particular interrupt service routine for a particular interrupt request 失效
标题翻译：用于选择性地调用特定中断请求的特定中断服务程序的方法和装置
公开(公告)号：US5862389A
公开(公告)日：1999-01-19
申请号：US778516
申请日：1997-01-03
申请人： James P. Kardach , Sung Soo Cho , Jayesh M. Joshi
发明人： James P. Kardach , Sung Soo Cho , Jayesh M. Joshi
IPC分类号： G06F9/48 , G06F13/24
CPC分类号： G06F9/4812 , G06F13/24
摘要： A circuit for selectively invoking a particular interrupt service routine to handle a particular interrupt request. The present invention includes a programmable register with one or more bits per interrupt request input. The present invention also includes interrupt selection logic which outputs a particular interrupt in response to an interrupt request input and data stored in the programmable register. The interrupt then invokes the associated interrupt service routine to handle the interrupt request. The present invention is used to choose the interrupt service routine to handle a particular interrupt request from any source within the computer system in any computer system operating mode.
摘要翻译：用于选择性地调用特定中断服务程序来处理特定中断请求的电路。本发明包括一个可编程寄存器，每个中断请求输入具有一个或多个位。本发明还包括响应于中断请求输入和存储在可编程寄存器中的数据输出特定中断的中断选择逻辑。然后中断调用相关的中断服务程序来处理中断请求。本发明用于在任何计算机系统操作模式中选择中断服务程序来处理来自计算机系统内的任何源的特定中断请求。

45. 发明授权

US5862349A Method and apparatus for docking and undocking a notebook computer 失效
标题翻译：用于对接和脱离笔记本电脑的方法和装置
公开(公告)号：US5862349A
公开(公告)日：1999-01-19
申请号：US754400
申请日：1996-11-21
申请人： Sung-Soo Cho , Diane M. Bryant , James P. Kardach , Feng Deng
发明人： Sung-Soo Cho , Diane M. Bryant , James P. Kardach , Feng Deng
IPC分类号： G06F13/12 , G06F1/16 , G06F3/00 , G06F13/40 , H01J3/00
CPC分类号： G06F13/4081 , G06F1/1632 , Y02B60/1228 , Y02B60/1235
摘要： Prior art quiet docking and undocking methods used an interface that was located within the notebook computer, thus adding to the cost, complexity, weight, and power consumption of the notebook computer. The present invention provides for an apparatus for quiet docking of a notebook computer to a docking station, including interface circuitry located within the docking station. The interface detects when the notebook computer has been inserted within the docking station, and correspondingly enables a switch such that a common system bus is coupled between the notebook computer and the docking station. The interface also generates events to allow a software routine to configure the notebook computer and docking station without prior user intervention. The interface also includes circuitry to detect an undock request, and correspondingly undock the computer such that a transaction occurring on the system bus is not affected.
摘要翻译：现有技术的安静对接和脱离方法使用位于笔记本计算机内的接口，从而增加笔记本计算机的成本，复杂性，重量和功率消耗。本发明提供了一种用于将笔记本计算机安静地对接到对接站的装置，包括位于坞站内的接口电路。该接口检测笔记本计算机何时被插入对接站内，并且相应地启用开关，使得公共系统总线耦合在笔记本计算机和对接站之间。该界面还生成事件，以允许软件程序配置笔记本电脑和扩展坞，无需用户干预。接口还包括检测未停靠请求的电路，并相应地使计算机取消停靠，使得系统总线上发生的事务不受影响。

46. 发明授权

US5630147A System management shadow port 失效
标题翻译：系统管理影子端口
公开(公告)号：US5630147A
公开(公告)日：1997-05-13
申请号：US601697
申请日：1996-02-15
申请人： Sham Datta , Jayesh Joshi , James P. Kardach
发明人： Sham Datta , Jayesh Joshi , James P. Kardach
IPC分类号： G06F1/32 , G06F11/00
CPC分类号： G06F1/3253 , G06F1/3203 , Y02B60/1235
摘要： A device and method for transferring data, address and status information concerning a former I/O bus cycle before a system management interrupt is initiated. A plurality of system management shadow registers samples information from a system bus. Such information is obtained by a register accessing the plurality of system management shadow registers through a common shadow port.
摘要翻译：一种用于在系统管理中断启动之前传送有关前一个I / O总线周期的数据，地址和状态信息的设备和方法。多个系统管理影子寄存器从系统总线采样信息。这样的信息通过通过公共影子端口访问多个系统管理影子寄存器的寄存器获得。

47. 发明授权

US5560002A Method of testing a microprocessor by masking of an internal clock signal 失效
标题翻译：通过屏蔽内部时钟信号来测试微处理器的方法
公开(公告)号：US5560002A
公开(公告)日：1996-09-24
申请号：US534596
申请日：1995-09-27
申请人： James P. Kardach , Tosaku Nakanishi , Jimmy S. Cheng
发明人： James P. Kardach , Tosaku Nakanishi , Jimmy S. Cheng
IPC分类号： G06F1/04 , G06F1/10 , G06F1/26 , G06F11/00 , G06F11/267 , G06F1/14
CPC分类号： G06F11/2236 , G06F1/04 , G06F1/10 , G06F1/26 , G06F11/004
摘要： An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.
摘要翻译：用于控制由计算机系统的处理单元使用的时钟信号的停止的装置和方法包括使用新颖的外部引脚，该引脚能够启动导致停止内部时钟信号的事件序列。本发明包括微代码引擎，其通过执行在指令边界上停止当前指令的一系列步骤来响应外部引脚的断言。然后，逻辑电路产生屏蔽由系统的锁相环产生的时钟信号的信号。中断机制也用于优先考虑外部信号在其他系统中断中的发生。中断机制确保处理器在总线周期的中间没有停止其时钟。

48. 发明申请

US20130297909A1 DYNAMIC CORE SWAPPING 有权
公开(公告)号：US20130297909A1
公开(公告)日：2013-11-07
申请号：US13938150
申请日：2013-07-09
申请人： Brian V. Belmont , Animesh Mishra , James P. Kardach
发明人： Brian V. Belmont , Animesh Mishra , James P. Kardach
IPC分类号： G06F15/80
CPC分类号： G06F9/4418 , G06F1/3228 , G06F1/3275 , G06F1/3293 , G06F9/3867 , G06F9/4401 , G06F12/0842 , G06F13/4282 , G06F15/80 , Y02D10/151
摘要： An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

49. 发明授权

US07598959B2 Display controller 有权
标题翻译：显示刷新装置和方法
公开(公告)号：US07598959B2
公开(公告)日：2009-10-06
申请号：US11169509
申请日：2005-06-29
申请人： James P. Kardach , David Williams , Achintya K. Bhowmik , Barnes Cooper
发明人： James P. Kardach , David Williams , Achintya K. Bhowmik , Barnes Cooper
IPC分类号： G09G1/06 , G09G5/00 , G09G5/39 , G06F3/038 , G06F13/14 , G06F13/372 , G06F1/00 , G06T17/00
CPC分类号： G09G5/006 , G09G3/3648 , G09G5/363 , G09G2330/021 , G09G2340/0435
摘要： Apparatus and systems, as well as methods and articles, may operate to update video display pixels. A video display bus can communicate data to a video display according to specified clock frequencies and a refresh time period. Power conservation can be enhanced by adjusting the specified clock frequencies and/or refresh time period to provide idle time on the video display bus.
摘要翻译：设备和系统以及方法和物品可以操作来更新视频显示像素。视频显示总线可以根据指定的时钟频率和刷新时间周期将数据传送到视频显示器。可以通过调整指定的时钟频率和/或刷新时间来提高功率节省，从而在视频显示总线上提供空闲时间。

50. 发明授权

US07461275B2 Dynamic core swapping 有权
标题翻译：动态核心交换
公开(公告)号：US07461275B2
公开(公告)日：2008-12-02
申请号：US11241376
申请日：2005-09-30
申请人： Brian V. Belmont , Animesh Mishra , James P. Kardach
发明人： Brian V. Belmont , Animesh Mishra , James P. Kardach
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F9/4418 , G06F1/3228 , G06F1/3275 , G06F1/3293 , G06F9/3867 , G06F9/4401 , G06F12/0842 , G06F13/4282 , G06F15/80 , Y02D10/151
摘要： An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.
摘要翻译：本发明的实施例是用于动态地交换处理器核心的技术。第一个核心有一个第一个指令集。第一个核心以第一个性能级别执行程序。当触发事件发生时，第一个内核停止执行程序。第二核心具有与第一指令集兼容的第二指令集，并且具有与第一性能级别不同的第二性能级别。当第一个核心执行程序时，第二个内核处于掉电状态。在第一核心停止执行程序之后，电路对第二核心供电，使得第二核心继续在第二性能级别执行程序。

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