专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US5058115A Fault tolerant computer memory systems and components employing dual level error correction and detection with lock-up feature 失效
标题翻译：故障容错计算机存储系统和组件采用双层错误校正和锁定功能检测
公开(公告)号：US5058115A
公开(公告)日：1991-10-15
申请号：US322255
申请日：1989-03-10
申请人： Robert M. Blake , Douglas C. Bossen , Chin-Long Chen , John A. Fifield , Howard L. Kalter , Tin-Chee Lo
发明人： Robert M. Blake , Douglas C. Bossen , Chin-Long Chen , John A. Fifield , Howard L. Kalter , Tin-Chee Lo
IPC分类号： G06F12/16 , G06F11/10
CPC分类号： G06F11/1052 , G06F11/1008
摘要： In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, clip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

42. 发明授权

US08902679B2 Memory array with on and off-state wordline voltages having different temperature coefficients 有权
标题翻译：具有不同温度系数的开状态和截止状态字线电压的存储器阵列
公开(公告)号：US08902679B2
公开(公告)日：2014-12-02
申请号：US13534096
申请日：2012-06-27
申请人： John A. Fifield , Mark D. Jacunski
发明人： John A. Fifield , Mark D. Jacunski
IPC分类号： G11C5/14 , G11C8/08 , H02J1/10
CPC分类号： G11C8/08 , G11C7/04 , G11C11/4085 , Y10T307/555
摘要： Disclosed is a memory array structure, where a wordline driver selectively applies a high on-state voltage (VWLH) or a low off-state voltage (VWLL) to a wordline. VWLH has a slightly negative temperature coefficient so that it is regulated as high as the gate dielectric reliability limits allow, whereas VWLL has a substantially neutral temperature coefficient. To accomplish this, the wordline driver is coupled to one or more voltage regulation circuits. In one embodiment, the wordline driver is coupled to a single voltage regulation circuit, which incorporates a single voltage reference circuit having a single output stage that outputs multiple reference voltages. Also disclosed is a voltage reference circuit, which can be incorporated into the voltage regulation circuit of a memory array structure, as described, or, alternatively, into any other integrated circuit structure requiring voltages with different temperature coefficients. Also disclosed is a method of operating a memory array structure.
摘要翻译：公开了一种存储器阵列结构，其中字线驱动器选择性地将高导通状态电压（VWLH）或低关态电压（VWLL）施加到字线。 VWLH具有轻微的负温度系数，使得其受到栅极介电可靠性限制允许的高度调节，而VWLL具有基本上中性的温度系数。为了实现这一点，字线驱动器耦合到一个或多个电压调节电路。在一个实施例中，字线驱动器耦合到单个电压调节电路，其包括具有输出多个参考电压的单个输出级的单个电压参考电路。还公开了一种电压参考电路，其可以结合到如所描述的存储器阵列结构的电压调节电路中，或者可以并入任何其它需要具有不同温度系数的电压的集成电路结构。还公开了一种操作存储器阵列结构的方法。

43. 发明申请

US20140025915A1 PROTECTION OF ONE-TIME PROGRAMMABLE (OTP) MEMORY 有权
标题翻译：保护一次性可编程（OTP）存储器
公开(公告)号：US20140025915A1
公开(公告)日：2014-01-23
申请号：US13555412
申请日：2012-07-23
申请人： John A. Fifield , Gerald P. Pomichter, JR. , Jeffrey S. Zimmerman
发明人： John A. Fifield , Gerald P. Pomichter, JR. , Jeffrey S. Zimmerman
IPC分类号： G06F12/14
CPC分类号： G06F12/1458 , G11C7/24 , G11C8/20 , G11C16/00 , G11C17/16 , G11C17/18
摘要： Aspects of the invention provide for masking a current profile of a one-time programmable (OTP) memory. In one embodiment, a circuit includes: a first one-time programmable (OTP) memory configured to receive a data input for a plurality of address fields; and a second OTP memory configured to receive an inverse of the data input for a plurality of address fields, wherein a current profile for a programming supply for the first OTP memory and the second OTP memory is masked, such that the data input for the first OTP memory is undetectable.
摘要翻译：本发明的方面提供了掩蔽一次性可编程（OTP）存储器的当前简档。在一个实施例中，电路包括：被配置为接收多个地址字段的数据输入的第一一次可编程（OTP）存储器; 以及第二OTP存储器，被配置为接收对于多个地址字段的数据输入的反相，其中屏蔽用于第一OTP存储器和第二OTP存储器的编程电源的当前简档，使得为第一 OTP内存不可检测。

44. 发明授权

US08035452B2 Structure for transforming an input voltage to obtain linearity between input and output functions and system and method thereof 有权
标题翻译：用于变换输入电压以获得输入和输出功能之间的线性的结构及其系统及方法
公开(公告)号：US08035452B2
公开(公告)日：2011-10-11
申请号：US12057686
申请日：2008-03-28
申请人： Wagdi W. Abadeer , John A. Fifield , Stephen D. Wyatt
发明人： Wagdi W. Abadeer , John A. Fifield , Stephen D. Wyatt
IPC分类号： H03L7/00 , H03B5/08 , H03C3/22
CPC分类号： H03L7/099
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a first structure for determining a non-linear characteristic of the input voltage to the output frequency response, the first design structure providing a tunneling-based current relationship with the input voltage. Also disclosed is a system and a method of implementing such structure.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括用于确定输入电压对输出频率响应的非线性特性的第一结构，第一设计结构提供与输入电压的基于隧道的电流关系。还公开了一种实现这种结构的系统和方法。

45. 发明授权

US07894291B2 Circuit and method for controlling a standby voltage level of a memory 有权
标题翻译：用于控制存储器的待机电压电平的电路和方法
公开(公告)号：US07894291B2
公开(公告)日：2011-02-22
申请号：US11162847
申请日：2005-09-26
申请人： George M. Braceras , John A. Fifield , Harold Pilo
发明人： George M. Braceras , John A. Fifield , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147
摘要： A memory is provided which can be operated at an active rate of power consumption in an active operational mode and at a predetermined reduced rate of power consumption in a standby operational mode. The memory includes a current generating circuit which is operable to supply a predetermined magnitude of current to a sample power supply input terminal of a sample memory cell representative of memory cells of the memory, the predetermined magnitude of current corresponding to the predetermined reduced rate of power consumption. A voltage follower circuit is operable to output a standby voltage level equal to a voltage level at the sample power supply input terminal when the predetermined magnitude of current is supplied thereto. A memory cell array of the memory is operable to store data. In the standby operational mode, a switching circuit is operable to supply power at the standby voltage level to a power supply input terminal of the memory cell array. This permits data to remain stored in the memory during the standby mode. During an active operational mode, the switching circuit is operable to connect the power supply input terminal at the power supply to supply power at the active voltage level to the memory cell array. During the active operational mode, data can be stored into the memory cell array and retrieved from the memory cell array.
摘要翻译：提供一种存储器，其可以在主动操作模式中以在备用操作模式中以预定的降低的功率消耗速率以有效的功率消耗速率操作。存储器包括电流产生电路，其可操作以向代表存储器的存储器单元的采样存储单元的采样电源输入端提供预定大小的电流，与预定的降低的功率比相对应的预定电流值消费。电压跟随器电路可操作以当提供预定电流大小时输出等于采样电源输入端的电压电平的备用电压电平。存储器的存储单元阵列可操作以存储数据。在待机操作模式中，切换电路可操作以将备用电压电平的电力提供给存储单元阵列的电源输入端。这在待机模式期间允许数据保存在存储器中。在有效操作模式期间，开关电路可操作地连接电源处的电源输入端，以将有源电压电平的电力提供给存储单元阵列。在主动操作模式期间，可将数据存储到存储单元阵列中并从存储单元阵列检索。

46. 发明申请

US20110002188A1 Apparatus for Nonvolatile Multi-Programmable Electronic Fuse System 有权
标题翻译：非易失性多可编程电子保险丝系统装置
公开(公告)号：US20110002188A1
公开(公告)日：2011-01-06
申请号：US12498175
申请日：2009-07-06
申请人： Howard H. Chen , John A. Fifield , Louis C. Hsu
发明人： Howard H. Chen , John A. Fifield , Louis C. Hsu
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C17/16
摘要： Electronic fuse (e-fuse) systems with multiple reprogrammability are provided. In one aspect, a reprogrammable e-fuse system is provided that includes a first e-fuse string; a second e-fuse string; a selector connected to both the first e-fuse string and the second e-fuse string configured to alternately select an e-fuse from the first e-fuse string or the second e-fuse string to be programmed; and a comparator connected to both the first e-fuse string and the second e-fuse string configured to compare a voltage across the first e-fuse string to a voltage across the second e-fuse string to determine a programming state of the e-fuse system.
摘要翻译：提供具有多重重新编程能力的电子保险丝（e-fuse）系统。在一个方面，提供了一种可再编程电子熔丝系统，其包括第一电熔丝串; 第二个电熔丝串; 连接到第一电熔丝串和第二电熔丝串的选择器，被配置为交替地从要编程的第一电熔丝串或第二电熔丝串中选择电熔丝; 以及连接到第一电熔丝串和第二电熔丝串两者的比较器，被配置为将第一电熔丝串两端的电压与跨第二电熔丝串的电压进行比较，以确定电子熔丝串的编程状态，保险丝系统

47. 发明申请

US20090153172A1 STRUCTURE FOR INDICATING STATUS OF AN ON-CHIP POWER SUPPLY SYSTEM 有权
标题翻译：表示片上电源系统状态的结构
公开(公告)号：US20090153172A1
公开(公告)日：2009-06-18
申请号：US12114070
申请日：2008-05-02
申请人： Darren Anand , John A. Fifield , Kevin W. Gorman
发明人： Darren Anand , John A. Fifield , Kevin W. Gorman
IPC分类号： G01R31/40 , G01R31/28
CPC分类号： G01R31/31721 , G06F17/505 , G06F2217/78
摘要： A design structure embodied in a machine readable medium used in a design process includes a system for indicating status of an on-chip power supply system with multiple power supplies, having a power system status register for receiving digital compliance signals, each compliance signal associated with one of the multiple power supplies, and having an associated compliance level, wherein each digital compliance signal indicates whether its associated power supply is operating at the associated compliance level, and wherein the power system status register generates a power supply status signal based on the digital compliance signals indicating status of the digital compliance signals; and an output for outputting the power supply status signal, wherein if a power supply is operating at its associated compliance level, the power supply status signal indicates that the power supply is passing, otherwise the power supply status signal indicates that the power supply is failing.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括用于指示具有多个电源的片上电源系统的状态的系统，具有用于接收数字符合性信号的电力系统状态寄存器，与多个电源中的一个并且具有相关联的合规级别，其中每个数字符合信号指示其相关联的电源是否在相关联的合规级别操作，并且其中电力系统状态寄存器基于数字信号产生电源状态信号指示数字符合信号状态的符合性信号; 以及用于输出电源状态信号的输出，其中如果电源正在其相关联的顺应性水平下操作，则电源状态信号指示电源正在通过，否则电源状态信号指示电源发生故障。

48. 发明授权

US07499308B2 Programmable heavy-ion sensing device for accelerated DRAM soft error detection 有权
标题翻译：用于加速DRAM软错误检测的可编程重离子感测装置
公开(公告)号：US07499308B2
公开(公告)日：2009-03-03
申请号：US11689096
申请日：2007-03-21
申请人： Howard H. Chen , John A. Fifield , Louis L. Hsu , Henry H. K. Tang
发明人： Howard H. Chen , John A. Fifield , Louis L. Hsu , Henry H. K. Tang
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G01R31/31816 , G11C11/401 , G11C11/40615 , G11C11/4078 , G11C11/4091 , G11C29/026 , G11C29/028 , G11C29/50 , G11C29/52 , G11C2029/5002
摘要： Aspects of the invention relate to a programmable heavy-ion sensing device for accelerated DRAM soft error detection. Design of a DRAM-based alpha particle sensing apparatus is preferred to be used as an accelerated on-chip SER test vehicle. The sensing apparatus is provided with programmable sensing margin, refresh rate, and supply voltage to achieve various degree of SER sensitivity. In addition, a dual-mode DRAM array is proposed so that at least a portion of the array can be used to monitor high-energy particle activities during soft-error detection (SED) mode.
摘要翻译：本发明的方面涉及用于加速DRAM软错误检测的可编程重离子感测装置。优选将基于DRAM的α粒子感测装置的设计用作加速片上SER测试车辆。该感测装置具有可编程的感应余量，刷新率和电源电压，以达到SER灵敏度的各种程度。另外，提出了双模DRAM阵列，使得阵列的至少一部分可以用于在软错误检测（SED）模式期间监视高能量粒子活动。

49. 发明授权

US07495950B2 Voltage controlled static random access memory 失效
标题翻译：电压控制静态随机存取存储器
公开(公告)号：US07495950B2
公开(公告)日：2009-02-24
申请号：US11926689
申请日：2007-10-29
申请人： John A. Fifield , Harold Pilo
发明人： John A. Fifield , Harold Pilo
IPC分类号： G11C11/00
CPC分类号： G11C8/08 , G11C11/413
摘要： A static random access memory (SRAM) comprising a plurality of SRAM cells, a plurality of wordlines (WL0-WLN) and a voltage regulator for driving the wordlines with a wordline voltage signal (VWLP). The wordline voltage signal is determined so as to reduce the likelihood of occurrence of read-disturbances and other memory instabilities. In one embodiment, the wordline voltage signal is determined as a function of the metastability voltage (VMETA) of the SRAM cells and an adjusted most positive down level voltage (VAMPDL) that is a function of a predetermined voltage margin (VM) and a most positive down level voltage (VMPDL) that corresponds to the read-disturb voltage of the SRAM cells.
摘要翻译：包括多个SRAM单元，多个字线（WL0-WLN）和用于用字线电压信号（VWLP）驱动字线的电压调节器的静态随机存取存储器（SRAM）。确定字线电压信号以便减少发生读取干扰和其它存储器不稳定性的可能性。在一个实施例中，字线电压信号被确定为SRAM单元的亚稳态电压（VMETA）的函数，以及作为预定电压余量（VM）的函数的经调整的最正向下电平电压（VAMPDL）对应于SRAM单元的读取 - 干扰电压的正向下电平电压（VMPDL）。

50. 发明申请

US20090021289A1 Voltage Detection Circuit in an Integrated Circuit and Method of Generating a Trigger Flag Signal 有权
标题翻译：集成电路中的电压检测电路和产生触发标志信号的方法
公开(公告)号：US20090021289A1
公开(公告)日：2009-01-22
申请号：US12242114
申请日：2008-09-30
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
IPC分类号： H03L7/00
CPC分类号： H03K5/153
摘要： An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.
摘要翻译：一种集成电路，其包括用于产生触发标志信号的至少一个隧道装置电压检测电路。隧道装置电压检测电路包括接收电源电压并具有对应的相应的第一和第二内部节点输出电压的第一和第二分压器。第一和第二分压器被配置为使得第一输出电压相对于电源电压是线性的，并且使得第二输出电压相对于电源电压是非线性的。随着电源电压上升，第一和第二输出电压的曲线在特定电压下交叉。运算放大器电路检测第一和第二输出电压何时相等，并且响应于此，输出指示电源电压达到一定水平的触发信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式