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    • 43. 发明授权
    • Mechanism to control di/dt for a microprocessor
    • 控制微处理器的di / dt的机制
    • US06636976B1
    • 2003-10-21
    • US09608748
    • 2000-06-30
    • Edward T. GrochowskiDavid SagerVivek TiwariIan YoungDavid J. Ayers
    • Edward T. GrochowskiDavid SagerVivek TiwariIan YoungDavid J. Ayers
    • G06F132
    • G06F1/3237G06F1/28G06F1/3203Y02D10/128
    • The present invention provides a mechanism for adjusting the activity of an integrated digital circuit such as a processor to reduce voltage changes attributable to current changes triggered by clock gating. The processor includes one or more functional units and a current control circuit that monitors activity states of the processor's functional units to estimate the current consumed over n clock cycles. The current control circuit estimates the current change for a given clock cycle from the n activity states and compares the estimated current change with first and second thresholds. The processors activity is decreased if the estimated current change is greater than the first threshold, and the processor activity is decreased if the estimated current change is less than the second threshold.
    • 本发明提供一种用于调整诸如处理器的集成数字电路的活动性的机构,以减少归因于由时钟门控触发的电流变化的电压变化。 处理器包括一个或多个功能单元和电流控制电路,其监视处理器的功能单元的活动状态以估计在n个时钟周期内消耗的电流。 电流控制电路从n个活动状态估计给定时钟周期的电流变化,并将估计的电流变化与第一和第二阈值进行比较。 如果估计的电流变化大于第一阈值,则处理器活动减小,并且如果估计的电流变化小于第二阈值,则处理器活动性降低。
    • 47. 发明授权
    • Spin hall effect memory
    • 旋转厅效果记忆
    • US09281467B2
    • 2016-03-08
    • US13537541
    • 2012-06-29
    • Sasikanth ManipatruniDmitri NikonovIan Young
    • Sasikanth ManipatruniDmitri NikonovIan Young
    • H01L43/08H01L49/02H01L27/22G11C11/18
    • H01L43/08G11C11/161G11C11/1655G11C11/1659G11C11/1673G11C11/1675G11C11/18H01L27/222H01L27/228H01L28/65
    • An embodiment of the invention includes a memory cell having a magnet layer coupled to a metal layer and read line. The metal layer is also coupled to write and sense lines. During a write operation charge current is supplied to the metal layer via the write line and induces spin current and a magnetic state within the magnet layer based on the spin Hall effect. During a read operation read current is supplied, via the read line, to the magnet layer and then the metal layer and induces another spin current, within the metal layer, that generates an electric field and voltage, based on inverse spin Hall effect, at a sense node coupled to the sense line. The voltage polarity is based on the aforementioned magnetic state. The memory operates with a low supply voltage to drive charge, read, and spin currents. Other embodiments are described herein.
    • 本发明的实施例包括具有耦合到金属层和读取线的磁体层的存储单元。 金属层也耦合到写入和感测线。 在写入操作期间,通过写入线将充电电流提供给金属层,并且基于旋转霍尔效应引起磁体层内的自旋电流和磁状态。 在读取操作期间,读取电流通过读取线被提供给磁体层,然后被提供给金属层,并且在金属层内引起另一自旋电流,其基于反旋转霍尔效应产生电场和电压 耦合到感测线的感测节点。 电压极性基于上述磁状态。 存储器以低电源电压运行,以驱动电荷,读数和自旋电流。 本文描述了其它实施例。
    • 49. 发明申请
    • Mutual charge cancelling sample-reset loop filter for phase locked loops
    • 用于锁相环的相互电荷消除采样复位环路滤波器
    • US20090243660A1
    • 2009-10-01
    • US12079786
    • 2008-03-28
    • Hyung-Jin LeeIan Young
    • Hyung-Jin LeeIan Young
    • G06G7/18H03D13/00
    • H03L7/0893H03L7/093H03L7/18
    • In general, in one aspect, an apparatus includes a phase frequency detector, a charge pump, a voltage controlled oscillator, an integral capacitor to maintain an integral charge and provide an integral voltage, and a mutual-charge canceling sample reset (MCSR) capacitor to maintain a proportional charge and provide a proportional voltage each reference clock cycle. The MCSR includes a first proportional capacitor, a second proportional capacitor in parallel to, and having substantially identical capacitance value as, the first proportional capacitor, a first set of switches to provide direct coupling of the first and second proportional capacitors, and a second set of switches to provide cross coupling of the first and second proportional capacitors. The first and second set of switches alternatively turn on and off every reference clock cycle so that set of switches coupling the first and second proportional capacitors alternates every reference clock cycle.
    • 通常,在一个方面,一种装置包括相位频率检测器,电荷泵,压控振荡器,用于保持积分电荷并提供积分电压的积分电容器,以及互电容取样器复位(MCSR)电容器 保持比例电荷并提供比例电压每个参考时钟周期。 MCSR包括与第一比例电容器并联并且具有与第一比例电容器基本相同的电容值的第一比例电容器,第二比例电容器,提供第一和第二比例电容器的直接耦合的第一组开关,以及第二组 的开关以提供第一和第二比例电容器的交叉耦合。 第一组和第二组开关交替地接通和关断每个参考时钟周期,使得耦合第一和第二比例电容器的开关组在每个参考时钟周期交替。