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41. 发明授权

US06233639B1 Memory card utilizing two wire bus 失效
标题翻译：存储卡采用两条总线
公开(公告)号：US06233639B1
公开(公告)日：2001-05-15
申请号：US09225524
申请日：1999-01-04
申请人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg , Clarence R. Ogilvie , Paul C. Stabler
发明人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg , Clarence R. Ogilvie , Paul C. Stabler
IPC分类号： G06F1300
CPC分类号： G11C5/066
摘要： A serial bus and connection to a device on a computer system through a system memory controller is provided on a memory card having a DSP and a memory bus controller to allow the DSP on the memory card to gain access to the system device without using the system memory bus. The serial bus is a two wire serial bus connecting the device to the DSP through the system memory controller. If more than one memory card is present with DSPs or more than one device is contending for access, the system memory controller or arbitrate the access of each memory card or contending device. In such case the serial bus will signal the system memory controller when it wants access to the particular device, and the system memory controller will act as arbitrator to grant or not grant access to the particular memory card or device requesting access. If access is granted the bus memory controller outputs the required control or command word on the serial bus followed by the address and the required data. This serial information is received by the system memory controller which packets it, and, upon completion, outputs the information rapidly on a parallel bus, e.g. a PCI bus to the device which needs the information.
摘要翻译：在具有DSP和存储器总线控制器的存储卡上提供串行总线和通过系统存储器控制器与计算机系统上的设备的连接，以允许存储卡上的DSP访问系统设备而不使用系统内存总线串行总线是通过系统存储器控制器将设备连接到DSP的双线串行总线。如果多个存储卡存在于DSP或多于一个设备正在争取访问，则系统存储器控制器或仲裁每个存储卡或竞争设备的访问。在这种情况下，当串行总线想要访问特定设备时，串行总线将向系统存储器控制器发信号通知，并且系统存储器控制器将充当仲裁器以授予或不授予对请求访问的特定存储卡或设备的访问权限。如果访问被授予，总线存储器控制器在串行总线上输出所需的控制或命令字，然后输出地址和所需的数据。该串行信息由系统存储器控制器接收，该系统存储器控制器对其进行分组，并且在完成时，在并行总线上快速地输出信息，例如， PCI总线到需要信息的设备。

42. 发明授权

US06178517B1 High bandwidth DRAM with low operating power modes 失效
标题翻译：具有低工作功率模式的高带宽DRAM
公开(公告)号：US06178517B1
公开(公告)日：2001-01-23
申请号：US09121933
申请日：1998-07-24
申请人： Claude L. Bertin , Timothy J. Dell , Erik L. Hedberg , Mark W. Kellogg
发明人： Claude L. Bertin , Timothy J. Dell , Erik L. Hedberg , Mark W. Kellogg
IPC分类号： G06F1200
CPC分类号： G06F13/1684 , Y02D10/14
摘要： A high bandwidth DRAM is provided with two separate bus networks connecting the DRAM to a processor. One bus network is a high speed (e.g., 500 MHZ) 8:1 or 16:1 multiplexed I/O bus and the second is a slower (e.g., 64-bit) bus. The high-speed bus is used for example for graphic intensive applications which require fast access to large numbers of bits in the DRAM memory array. This of course results in higher power requirements. Since, not all applications require such large amounts of data to be transferred between the DRAM and the processor, the slower bus is provided for these less demanding applications such as word processors, spreadsheets, and the like. The slower bus requires less power to operate and therefore results in a power saving mode which, among other things, facilitates longer battery life.
摘要翻译：高带宽DRAM具有将DRAM连接到处理器的两个单独的总线网络。一个总线网络是高速（例如，500MHz）8：1或16：1多路复用I / O总线，第二个是较慢（例如，64位）总线。例如，高速总线用于需要快速访问DRAM存储器阵列中大量位的图形密集型应用。这当然会导致更高的功率需求。由于并非所有应用都需要在DRAM和处理器之间传输大量数据，所以为这些不太要求苛刻的应用程序提供较慢的总线，例如文字处理器，电子表格等。较慢的总线需要更少的功率来进行操作，因此导致省电模式，其中尤其有助于延长电池寿命。

43. 发明授权

US5896404A Programmable burst length DRAM 失效
标题翻译：可编程突发长度DRAM
公开(公告)号：US5896404A
公开(公告)日：1999-04-20
申请号：US833371
申请日：1997-04-04
申请人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
发明人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
IPC分类号： G06F12/16 , G06F11/10 , G11C7/10 , G11C11/401 , G11C29/42 , G11C29/00
CPC分类号： G06F11/1008 , G11C7/1018 , G06F11/1052
摘要： A Dynamic Random Access Memory (DRAM) with a burst length programmable as eight (8) or nine (9) bytes. The DRAM array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is programmed in Normal mode, the burst length is 8 and the entire array address space is available for data storage. When the DRAM is programmed for error checking (ECC mode), the burst length is nine and the array is reconfigured with part of the array providing the ninth byte. The DRAM's address space is reduced by one-eighth in ECC mode. Preferably, all nine locations are in the same page, with each page being divided into eight equal portions. In Normal mode all eight equal portions are data storage; and, in ECC mode, seven-eighths of the page is data storage, the remaining one eighth being assigned to check bit storage.
摘要翻译：具有可编程为八（8）或九（9）字节的突发长度的动态随机存取存储器（DRAM）。 DRAM阵列分为两个或更多个子阵列，子阵列单元以可寻址的行和列排列。当DRAM在正常模式下编程时，突发长度为8，整个阵列地址空间可用于数据存储。当DRAM被编程用于错误检查（ECC模式）时，突发长度为9，并且阵列被配置为提供第九个字节的阵列的一部分。在ECC模式下，DRAM的地址空间减少了八分之一。优选地，所有九个位置在同一页面中，每个页面被分成八个相等的部分。在正常模式下，所有八个相等的部分都是数据存储; 并且在ECC模式中，页面的七分之一是数据存储，剩下的八分之一被分配给校验位存储。

44. 发明授权

US07394268B2 Carrier for test, burn-in, and first level packaging 失效
标题翻译：用于测试，老化和一级包装的载体
公开(公告)号：US07394268B2
公开(公告)日：2008-07-01
申请号：US11531140
申请日：2006-09-12
申请人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
发明人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
IPC分类号： G01R31/02
CPC分类号： G01R31/2867 , G11C5/04 , G11C29/06 , G11C29/1201 , G11C29/48 , G11C29/56016 , G11C29/785 , G11C2029/2602 , G11C2029/5602 , H01L22/22 , H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier.
摘要翻译：在载体上提供多个半导体器件用于测试或烧录。然后将载体切割以提供单个芯片上载波部件或多芯片载波部件。载体用作每个芯片的第一级封装。因此，载体用于测试和烧录和包装的双重目的。可以在每个芯片或载体上提供诸如内置自检引擎的引线减少机构，并且连接到载体的触点用于测试和老化步骤。切割后的最终包装包括至少一个已知的良好的模具，并且可以包括载体上的芯片阵列，例如SIMM或DIMM。最终的包装也可以是一堆芯片，每个芯片都安装在单独的载体上。堆叠的载体通过沿着堆叠的侧面安装的基板彼此连接，该基板沿着每个载体的边缘电连接到焊盘一排。

45. 发明授权

US06467053B1 Captured synchronous DRAM fails in a working environment 有权
标题翻译：捕获的同步DRAM在工作环境中失败
公开(公告)号：US06467053B1
公开(公告)日：2002-10-15
申请号：US09340804
申请日：1999-06-28
申请人： Brian J. Connolly , Steven A. Grundon , Bruce G. Hazelzet , Mark W. Kellogg , James R. Mallabar
发明人： Brian J. Connolly , Steven A. Grundon , Bruce G. Hazelzet , Mark W. Kellogg , James R. Mallabar
IPC分类号： G06F11277
CPC分类号： G11C29/56 , G11C29/56012 , G11C2029/5602
摘要： A Synchronous DRAM memory test assembly that converts a normal PC or Workstation with a synchronous bus into a memory tester. The test assembly may be split into two segments: a diagnostic card and an adapter card to limit mechanical load on the system socket as well as permit varying form factors. This test assembly architecture supports memory bus speeds of 66 MHz and above, and provides easy access for a logic analyzer. The test assembly supports Registered and Unbuffered Synchronous DRAM products. The test assembly permits good and questionable synchronous modules to be compared using an external logic analyzer. It permits resolution of in-system fails that occur uniquely in system environments and may be otherwise difficult or impossible to replicate. The test assembly re-drives the system clocks with a phase lock loop (PLL) buffer to a memory module socket on the test assembly to permit timing adjustments to minimize the degradation to the system's memory bus timings due to the additional wire length and loading. The test assembly is programmable to adjust to varying bus timings such as: CAS (column address strobe) Latencies and Burst Length variations. It is designed with Field Programmable Gate Arrays (FPGAs) to allow for changes internally without modifying the test assembly.
摘要翻译：同步DRAM存储器测试组件，其将具有同步总线的普通PC或工作站转换为存储器测试器。测试组件可以分为两个部分：诊断卡和适配卡，以限制系统插座上的机械负载以及允许变化的外形尺寸。该测试组件架构支持66 MHz及以上的内存总线速度，并为逻辑分析仪提供方便的访问。测试组件支持注册和非缓冲同步DRAM产品。测试组件允许使用外部逻辑分析仪比较好的和有问题的同步模块。它允许解决在系统环境中唯一发生的系统内故障，并且可能难以或不可能复制。测试组件使用锁相环（PLL）缓冲区将系统时钟重新驱动到测试组件上的存储器模块插槽，以允许定时调整，以最大限度地减少系统的存储器总线时序由于额外的电线长度和负载而的劣化。测试组件可编程为适应变化的总线时序，例如：CAS（列地址选通）延迟和突发长度变化。它设计有现场可编程门阵列（FPGA），可在内部进行更改，无需修改测试组件。

46. 发明授权

US5513135A Synchronous memory packaged in single/dual in-line memory module and method of fabrication 失效
标题翻译：封装在单/双列直插式存储器模块中的同步存储器和制造方法
公开(公告)号：US5513135A
公开(公告)日：1996-04-30
申请号：US349154
申请日：1994-12-02
申请人： Timothy J. Dell , Lina S. Farah , George C. Feng , Mark W. Kellogg
发明人： Timothy J. Dell , Lina S. Farah , George C. Feng , Mark W. Kellogg
IPC分类号： G11C5/00 , G11C5/06
CPC分类号： G11C5/06 , G11C5/04
摘要： Multiple synchronous dynamic random access memories (SDRAMs) are packaged in a single or a dual in-line memory module to have similar physical and architectural characteristics of dynamic random access memories (DRAMs) packaged in single/dual in-line memory modules. A 168 pin SDRAM DIMM family is presented which requires no modification of existing connector, planar or memory controller components. The 168 pin SDRAM DIMM family includes 64 bit non-parity, 72 bit parity, 72 bit ECC and 80 bit ECC memory organizations. Special placement and wiring of decoupling capacitors about the SDRAMs and the buffer chips contained within the module are also presented to reduce simultaneous switching noises during read and write operations. A special wiring scheme for the decoupling capacitors is employed to reduce wiring inductance.
摘要翻译：多个同步动态随机存取存储器（SDRAM）被封装在单个或双列直插存储器模块中，以具有封装在单/双列直插式存储器模块中的动态随机存取存储器（DRAM）的类似物理和架构特性。提供了一个168针SDRAM DIMM系列，不需要修改现有的连接器，平面或内存控制器组件。 168引脚SDRAM DIMM系列包括64位非奇偶校验，72位奇偶校验，72位ECC和80位ECC内存组织。还提供了关于SDRAM和包含在模块内的缓冲器芯片的去耦电容器的特殊放置和布线，以减少读写操作期间的同时开关噪声。采用去耦电容器的特殊布线方案来减少布线电感。

47. 发明授权

US5452429A Error correction code on add-on cards for writing portions of data words 失效
标题翻译：用于写入数据字部分的附加卡上的错误纠正码
公开(公告)号：US5452429A
公开(公告)日：1995-09-19
申请号：US154191
申请日：1993-11-17
申请人： Daniel P. Fuoco , Christopher M. Herring , Mark W. Kellogg , Jorge E. Lenta
发明人： Daniel P. Fuoco , Christopher M. Herring , Mark W. Kellogg , Jorge E. Lenta
IPC分类号： G06F12/16 , G06F11/10
CPC分类号： G06F11/1056 , G06F11/1052
摘要： The present invention provides a computer system and method of using the same. Add-on memory cards for the system are provided which cards have error correction code logic on the card, and logic to do partial writes of data words. The system has a central processing unit (CPU), a BUS interconnecting the CPU and the add-on memory cards. The CPU or associated components are configured to write data and read data from the add-on memory as several data bytes constituting data words. The system is further configured either within the CPU or as a separate function to generate parity bits associated with each of the bytes of data the CPU writes to the add-on memory and to read parity bits associated with data the CPU reads from the add-on memory and regenerate new parity bits and compare the newly generated parity bits with the original parity bits to detect data errors on data read from the add-on memory. The system itself does not contain error correction code (ECC). The add-on memory has ECC logic to identify any byte having a single bit error in the data bytes or the parity bits written by the CPU to the add-on memory and to correct all single bit errors in data read from the add-on memory to the CPU. The error correcting code includes logic to generate parity bits in the data bytes written by the CPU to the add-on memory and logic to compare the parity bits written by the CPU with those generated by the error correcting code logic.
摘要翻译：本发明提供一种计算机系统及其使用方法。提供系统的附加存储卡，哪些卡在卡上具有纠错码逻辑，以及进行数据字的部分写入的逻辑。该系统具有一个中央处理单元（CPU），一个连接CPU和附加存储卡的总线。 CPU或相关组件被配置为写入数据并从附加存储器读取数据作为构成数据字的几个数据字节。该系统进一步配置在CPU内或作为单独功能，以产生与CPU写入附加存储器的每个数据字节相关联的奇偶校验位，并读取与CPU从附加存储器读取的数据相关联的奇偶校验位，并重新生成新的奇偶校验位，并将新生成的奇偶校验位与原始奇偶校验位进行比较，以检测从附加存储器读取的数据上的数据错误。系统本身不包含纠错码（ECC）。附加存储器具有ECC逻辑，用于识别在数据字节中具有单个位错误的任何字节或由CPU向附加存储器写入的奇偶校验位，并校正从附件读取的数据中的所有单个位错误内存到CPU。纠错码包括在由CPU向附加存储器写入的数据字节中生成奇偶校验位的逻辑，以及将由CPU写入的奇偶校验位与由纠错码逻辑生成的奇偶校验位进行比较的逻辑。

48. 发明授权

US5412613A Memory device having asymmetrical CAS to data input/output mapping and applications thereof 失效
标题翻译：具有不对称CAS到数据输入/输出映射的存储器件及其应用
公开(公告)号：US5412613A
公开(公告)日：1995-05-02
申请号：US161279
申请日：1993-12-06
申请人： Duane E. Galbi , Michael P. Clinton , Mark W. Kellogg
发明人： Duane E. Galbi , Michael P. Clinton , Mark W. Kellogg
IPC分类号： G06F12/02 , G11C5/00 , G11C7/10 , G11C7/22 , G11C11/401 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： G11C7/22 , G11C7/1006
摘要： A semiconductor memory chip architecture is described implementing of a multi-bit data control function which enables independent control of at least a plurality of data bits via a single control signal. A logically organized memory chip is organized as a 2.sup.n x 4 chip in which one control (CAS0) signal enables a single data bit and another control (CAS1) signal enables the remaining three data bits. By organizing data control on chips in this manner, it becomes possible to optimize design modules such that a minimum number of control signals are used.
摘要翻译：描述了实现多位数据控制功能的半导体存储器芯片架构，其通过单个控制信号独立地控制至少多个数据位。逻辑组织的存储器芯片被组织为2nx 4芯片，其中一个控制（CAS0）信号使能单个数据位，另一个控制（CAS1）信号使能剩余的三个数据位。通过以这种方式组织芯片上的数据控制，可以优化设计模块，使得使用最少数量的控制信号。

49. 发明授权

US6118719A Self-initiated self-refresh mode for memory modules 失效
标题翻译：内存模块的自启动自刷新模式
公开(公告)号：US6118719A
公开(公告)日：2000-09-12
申请号：US81639
申请日：1998-05-20
申请人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg
发明人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A method and apparatus for selectively causing each bank of a number of banks of DRAMs of a DRAM memory card to enter into the self-refresh mode without affecting the operation of any other bank. In the computer system incorporating the SIMM or DIMM type DRAM cards, each bank of memory on each card has a RAS signal specific to that specific bank. One or more CAS signals are supplied across all of the memory banks, on all cards. Thus, each memory bank is accessed separately for a read/write operation by the RAS becoming active before the CAS becomes active; and refresh takes place by the CAS signal becoming active before the RAS signal becomes active. The number of clock cycles or refresh cycles between active RAS signals to each memory bank are counted. If RAS does not become active for N clock or refresh cycles, a signal is provided within each respective memory bank and that memory bank will immediately, or preferably after M additional clock or refresh cycles enter self-refresh mode without affecting the operation of any other bank. At the same time, the memory controller counts cycles of RAS inactivity for each DRAM bank it controls. A signal is also provided to a register to require a double read/write on the next active read/write cycle to that bank, for reactivating that bank from the self-refresh mode when RAS signal specific to that bank becomes active while CAS is inactive.
摘要翻译：一种用于选择性地使DRAM存储卡的DRAM组的每一组进入自刷新模式而不影响任何其他存储体的操作的方法和装置。在包含SIMM或DIMM型DRAM卡的计算机系统中，每张卡上的每一组存储器具有特定于该特定存储体的RAS信号。所有卡上的所有存储体都提供一个或多个CAS信号。因此，在CAS变为活动状态之前，RAS变为活动状态的每个存储体被单独访问用于读/写操作; 并且在RAS信号变为有效之前，CAS信号变为有效，刷新发生。计数到每个存储体的有效RAS信号之间的时钟周期数或刷新周期数。如果RAS对于N个时钟或刷新周期没有变为有效，则在每个相应的存储体内提供一个信号，并且该存储体将立即或优选地在M个附加时钟或刷新周期进入自刷新模式之后不影响任何其它的操作银行。同时，存储器控制器控制其控制的每个DRAM组的RAS不活动的周期。还向寄存器提供一个信号，要求在该存储体的下次有效读/写周期上进行双重读/写操作，当CAS不活动时，RAS特定于该存储体的信号变为活动状态时，从自刷新模式重新激活该存储体。

50. 发明授权

US5896346A High speed and low cost SDRAM memory subsystem 失效
标题翻译：高速和低成本的SDRAM内存子系统
公开(公告)号：US5896346A
公开(公告)日：1999-04-20
申请号：US918097
申请日：1997-08-21
申请人： Timothy J. Dell , George C. Feng , Mark W. Kellogg
发明人： Timothy J. Dell , George C. Feng , Mark W. Kellogg
IPC分类号： G11C11/407 , G06F12/00 , G11C7/10 , G11C7/22 , G11C11/401 , H05K1/02 , H05K1/14 , G11C8/00
CPC分类号： H05K1/0248 , G11C7/1072 , G11C7/22 , H05K1/14 , H05K2201/044 , H05K2201/10159 , H05K2201/10689
摘要： A synchronous dynamic random access memory subsystem includes two banks of connectors for receiving single or dual in-line memory modules. A clock is located in close proximity to the connectors and produces clock pulses having a known rise time. Clock wiring is placed between the clock and the connectors, and module wiring carries the clock pulses from the connectors to the memory. The wiring has an impedance and length such that the round trip delay time of clock pulses between the clock and the memory is less than the rise time of the clock pulses. The clock is preferably located between the two banks of connectors to reduce wiring length to a minimum and minimize coupled noise.
摘要翻译：同步动态随机存取存储器子系统包括用于接收单列或双列直插存储器模块的两组连接器。一个时钟靠近连接器，产生具有已知上升时间的时钟脉冲。时钟接线位于时钟和连接器之间，模块接线将时钟脉冲从连接器传送到存储器。布线具有阻抗和长度，使得时钟和存储器之间的时钟脉冲的往返延迟时间小于时钟脉冲的上升时间。时钟优选地位于两组连接器之间，以将布线长度最小化并使耦合噪声最小化。

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