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41. 发明授权

US07241703B2 Film forming method for semiconductor device 有权
标题翻译：半导体器件成膜方法
公开(公告)号：US07241703B2
公开(公告)日：2007-07-10
申请号：US10855328
申请日：2004-05-28
申请人： Masahiro Hikita , Yasuhiro Uemoto
发明人： Masahiro Hikita , Yasuhiro Uemoto
IPC分类号： H01L21/31
CPC分类号： C23C16/45523 , C23C16/402 , H01L21/02164 , H01L21/02271 , H01L21/31612 , H01L21/76834 , H01L21/76837
摘要： A method of forming films in a semiconductor device that can appropriately control a resistance value of a thin film resistance on an ozone TEOS film while preventing a metal thin film from remaining around a surface step unit after the metal thin film was dry etched. First, as shown in FIG. 1A, a step unit with the height of about 1 μm is formed by forming elements such as HBT on a semiconductor substrate made up of semi-insulating GaAs. Next, as shown in FIG. 1B, a first ozone TEOS film with the thickness of 900 nm by a Normal pressure CVD method using mixed gas of tetraethoxysilane with ozone. Then, a second ozone TEOS film with the thickness of 100 nm is formed by reducing the ozone concentration to 10 g/m3, while maintaining the substrate temperature at 350° C.
摘要翻译：在半导体器件中形成薄膜的方法，其可以在金属薄膜被干蚀刻之后防止金属薄膜残留在表面台阶单元周围，从而适当地控制臭氧TEOS薄膜上的薄膜电阻的电阻值。首先，如图1所示。在图1A中，通过在由半绝缘GaAs构成的半导体衬底上形成诸如HBT的元件来形成高度约为1um的台阶单元。接下来，如图3所示。 1B，使用四乙氧基硅烷与臭氧的混合气体，通过常压CVD法形成厚度为900nm的第一臭氧TEOS膜。然后，通过将臭氧浓度降低至10g / m 3，同时将基板温度保持在350℃，形成厚度为100nm的第二臭氧TEOS膜。

42. 发明授权

US07132703B2 Field-effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US07132703B2
公开(公告)日：2006-11-07
申请号：US11014893
申请日：2004-12-20
申请人： Masahiro Hikita , Manabu Yanagihara
发明人： Masahiro Hikita , Manabu Yanagihara
IPC分类号： H01I29/80
CPC分类号： H01L29/66462 , H01L29/7783
摘要： A field-effect transistor includes: a carrier supply layer supplying carriers; a Schottky contact layer forming a Schottky barrier; and an intermediate layer formed between the carrier supply layer and the Schottky contact layer. Here, the intermediate layer has an electron affinity which is higher than an electron affinity of the carrier supply layer but lower than an electron affinity of the Schottky contact layer.
摘要翻译：场效应晶体管包括：提供载体的载流子供应层; 形成肖特基势垒的肖特基接触层; 以及形成在载体供给层和肖特基接触层之间的中间层。这里，中间层的电子亲和力高于载流子供给层的电子亲和力，但低于肖特基接触层的电子亲和力。

43. 发明授权

US06797996B1 Compound semiconductor device and method for fabricating the same 失效
标题翻译：化合物半导体器件及其制造方法
公开(公告)号：US06797996B1
公开(公告)日：2004-09-28
申请号：US10445035
申请日：2003-05-27
申请人： Masahiro Hikita , Manabu Yanagihara , Tuyoshi Tanaka
发明人： Masahiro Hikita , Manabu Yanagihara , Tuyoshi Tanaka
IPC分类号： H01L29737
CPC分类号： H01L29/66318 , H01L29/0821 , H01L29/1004 , H01L29/365 , H01L29/7371
摘要： A compound semiconductor device includes an emitter layer, a base layer which is in contact with the emitter layer and formed of a first compound semiconductor, a collector layer which is in contact with the base layer and formed of a second compound semiconductor having a wider bandgap than that of the first compound semiconductor. In the device, a delta doped layer having a higher concentration of an impurity than that of the collector layer is formed at the heterojunction interface between the collector layer and the base layer or in a region of the collector layer located at about 10 nm or less from the heterojunction interface with the base layer.
摘要翻译：化合物半导体器件包括发射极层，与发射极层接触并由第一化合物半导体形成的基极层，与基极层接触并由具有较宽带隙的第二化合物半导体形成的集电极层比第一化合物半导体。在器件中，在集电极层和基极层之间的异质结界面处或在位于约10nm以下的集电极层的区域中形成杂质浓度高于集电极层的Δ掺杂层从与基层的异质结界面。

44. 发明授权

US08598628B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08598628B2
公开(公告)日：2013-12-03
申请号：US13231514
申请日：2011-09-13
申请人： Masahiro Hikita , Manabu Yanagihara
发明人： Masahiro Hikita , Manabu Yanagihara
IPC分类号： H01L29/72
CPC分类号： H01L29/42316 , H01L29/1066 , H01L29/2003 , H01L29/518 , H01L29/7786
摘要： A normally off semiconductor device with a reduced off-state leakage current, which is applicable to a power switching element, includes: a substrate; an undoped GaN layer formed above the substrate; an undoped AlGaN layer formed on the undoped GaN layer; a source electrode and a drain electrode, formed on the undoped GaN layer or the undoped AlGaN layer; a P-type GaN layer formed on the undoped AlGaN layer and disposed between the source electrode and the drain electrode; and a gate electrode formed on the P-type GaN layer, wherein the undoped GaN layer includes an active region including a channel and an inactive region not including the channel, and the P-type GaN layer is disposed to surround the source electrode.
摘要翻译：具有减小的截止状态漏电流的常闭半导体器件，其适用于功率开关元件，包括：衬底; 在衬底上形成未掺杂的GaN层; 在未掺杂的GaN层上形成未掺杂的AlGaN层; 源电极和漏电极，形成在未掺杂的GaN层或未掺杂的AlGaN层上; 形成在未掺杂的AlGaN层上并设置在源电极和漏电极之间的P型GaN层; 以及形成在所述P型GaN层上的栅电极，其中所述未掺杂的GaN层包括包括沟道的有源区和不包括所述沟道的非活性区，并且所述P型GaN层设置为围绕所述源电极。

45. 发明授权

US08723229B2 Semiconductor device and method of manufacturing the device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08723229B2
公开(公告)日：2014-05-13
申请号：US13182122
申请日：2011-07-13
申请人： Masahiro Hikita , Kenichiro Tanaka , Tetsuzo Ueda
发明人： Masahiro Hikita , Kenichiro Tanaka , Tetsuzo Ueda
IPC分类号： H01L21/02 , H01L29/66 , H01L29/15
CPC分类号： H01L29/66462 , H01L29/1066 , H01L29/2003 , H01L29/7787
摘要： In a manufacturing method of a semiconductor device, first, a first semiconductor layer, a second semiconductor layer, and a p-type third semiconductor layer are sequentially epitaxially grown on a substrate. After that, the third semiconductor layer is selectively removed. Then, a fourth semiconductor layer is epitaxially grown on the second semiconductor layer. Then, a gate electrode is formed on the third semiconductor layer.
摘要翻译：在半导体器件的制造方法中，首先，在衬底上依次外延生长第一半导体层，第二半导体层和p型第三半导体层。之后，选择性地去除第三半导体层。然后，在第二半导体层上外延生长第四半导体层。然后，在第三半导体层上形成栅电极。

46. 发明授权

US08450146B2 Transistor assembly and method for manufacturing the same 有权
标题翻译：晶体管组件及其制造方法
公开(公告)号：US08450146B2
公开(公告)日：2013-05-28
申请号：US13213967
申请日：2011-08-19
申请人： Kenichiro Tanaka , Tetsuzo Ueda , Hisayoshi Matsuo , Masahiro Hikita
发明人： Kenichiro Tanaka , Tetsuzo Ueda , Hisayoshi Matsuo , Masahiro Hikita
IPC分类号： H01L21/00 , H01L21/338 , H01L21/331 , H01L21/8222 , H01L21/336
CPC分类号： H01L29/7786 , H01L23/053 , H01L23/562 , H01L29/2003 , H01L29/225 , H01L29/452 , H01L29/475 , H01L2224/72 , H01L2924/01079 , H01L2924/12032 , H01L2924/00
摘要： A method for manufacturing a transistor assembly includes the steps of: (a) forming a transistor; (b) polishing a base substrate; and (c) securing the transistor of which the base substrate is polished to a support substrate. The step (a) is a step of forming a first semiconductor layer and a second semiconductor layer on a principle surface of the base substrate. The step (b) is a step of polishing a surface of the base substrate opposite to the principle surface. The step (c) is a step of securing the transistor on the support substrate in the presence of a stress applied on the base substrate in such a direction that a warp of the base substrate is reduced. The base substrate is made of a material different from that of the first semiconductor layer and the second semiconductor layer, and a tensile stress is applied on the second semiconductor layer.
摘要翻译：晶体管组件的制造方法包括以下步骤：（a）形成晶体管; （b）抛光基底; 和（c）将基底基板抛光的晶体管固定到支撑基板上。步骤（a）是在基底基板的主表面上形成第一半导体层和第二半导体层的工序。步骤（b）是对基材的与主面相反的表面进行研磨的工序。步骤（c）是在施加到基底基板上的应力存在下，使晶体管固定在支撑基板上，使基板的翘曲减小的方向。基底由不同于第一半导体层和第二半导体层的材料制成，并且在第二半导体层上施加拉伸应力。

47. 发明授权

US08441035B2 Field effect transistor and method of manufacturing the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US08441035B2
公开(公告)日：2013-05-14
申请号：US13150574
申请日：2011-06-01
申请人： Masahiro Hikita , Hidetoshi Ishida , Tetsuzo Ueda
发明人： Masahiro Hikita , Hidetoshi Ishida , Tetsuzo Ueda
IPC分类号： H01L29/778
CPC分类号： H01L29/7786 , H01L29/1066 , H01L29/2003 , H01L29/205 , H01L29/41766 , H01L29/66462 , H01L29/808
摘要： The present invention has an object to provide an FET and a method of manufacturing the FET that are capable of increasing the threshold voltage as well as decreasing the on-resistance. The FET of the present invention includes a first undoped GaN layer; a first undoped AlGaN layer formed on the first undoped GaN layer, having a band gap energy greater than that of the first undoped GaN layer; a second undoped GaN layer formed on the first undoped AlGaN layer; a second undoped AlGaN layer formed on the second undoped GaN layer, having a band gap energy greater than that of the second undoped GaN layer; a p-type GaN layer formed in the recess of the second undoped AlGaN layer; a gate electrode formed on the p-type GaN layer; and a source electrode and a drain electrode which are formed in both lateral regions of the gate electrode, wherein a channel is formed at the heterojunction interface between the first undoped GaN layer and the first undoped AlGaN layer.
摘要翻译：本发明的目的是提供一种能够增加阈值电压以及降低导通电阻的FET和FET的制造方法。本发明的FET包括第一未掺杂的GaN层; 形成在第一未掺杂的GaN层上的第一未掺杂的AlGaN层，其带隙能量大于第一未掺杂的GaN层的带隙能量; 形成在第一未掺杂的AlGaN层上的第二未掺杂的GaN层; 形成在所述第二未掺杂GaN层上的第二未掺杂AlGaN层，具有大于所述第二未掺杂GaN层的带隙能量的带隙能量; 形成在第二未掺杂AlGaN层的凹部中的p型GaN层; 形成在p型GaN层上的栅电极; 以及形成在所述栅电极的两个横向区域中的源电极和漏电极，其中在所述第一未掺杂的GaN层和所述第一未掺杂的AlGaN层之间的异质结界面处形成沟道。

48. 发明申请

US20110278540A1 FIELD-EFFECT TRANSISTOR 审中-公开
标题翻译：场效应晶体管
公开(公告)号：US20110278540A1
公开(公告)日：2011-11-17
申请号：US13111357
申请日：2011-05-19
申请人： Kenichiro Tanaka , Tetsuzo Ueda , Hisayoshi Matsuo , Masahiro Hikita
发明人： Kenichiro Tanaka , Tetsuzo Ueda , Hisayoshi Matsuo , Masahiro Hikita
IPC分类号： H01L29/12
CPC分类号： H01L29/7786 , H01L21/0237 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L29/1075 , H01L29/155 , H01L29/2003 , H01L29/475
摘要： Provided is a field-effect transistor which is capable of suppressing current collapse. An HEMT as the field-effect transistor includes: a first semiconductor layer made of a first nitride semiconductor; and a second semiconductor layer formed on the first semiconductor layer and made of a second nitride semiconductor having a greater band gap than a band gap of the first nitride semiconductor, wherein the first semiconductor layer includes a region in which a threading dislocation density increases in a stacking direction.
摘要翻译：提供能够抑制电流塌陷的场效应晶体管。作为场效应晶体管的HEMT包括：由第一氮化物半导体构成的第一半导体层; 以及第二半导体层，形成在所述第一半导体层上并且由具有比所述第一氮化物半导体的带隙大的带隙的第二氮化物半导体构成，其中所述第一半导体层包括其中穿透位错密度增加的区域层叠方向

49. 外观设计

USD685722S1 Tire for motorcycle 有权
公开(公告)号：USD685722S1
公开(公告)日：2013-07-09
申请号：US29433015
申请日：2012-09-25
申请人： Masahiro Hikita
设计人： Masahiro Hikita

50. 外观设计

USD671485S1 Tire for motorcycle 有权
标题翻译：摩托车轮胎
公开(公告)号：USD671485S1
公开(公告)日：2012-11-27
申请号：US29417593
申请日：2012-04-05
申请人： Masahiro Hikita
设计人： Masahiro Hikita

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