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41. 发明申请

US20100281446A1 Integrated Circuit Design using DFM-Enhanced Architecture 有权
标题翻译：使用DFM增强架构的集成电路设计
公开(公告)号：US20100281446A1
公开(公告)日：2010-11-04
申请号：US12708242
申请日：2010-02-18
申请人： Yung-Chin Hou , Lee-Chung Lu , Li-Chun Tien , Yi-Kan Cheng , Chun-Hui Tai , Ta-Pen Guo , Yuan-Te Hou
发明人： Yung-Chin Hou , Lee-Chung Lu , Li-Chun Tien , Yi-Kan Cheng , Chun-Hui Tai , Ta-Pen Guo , Yuan-Te Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell.
摘要翻译：集成电路库包括具有第一左边界和第一右边界的第一标准单元，以及具有第二左边界和第二右边界的第二标准单元。第一标准细胞和第二标准细胞具有相同的细胞变体。第一标准单元中的第一有源区具有与第二标准单元中的第二有源区不同的扩散长度。第一有源区和第二有源区是由表示第一标准单元和第二标准单元的相同电路图的相同分量表示的相应有源区。

42. 发明授权

US07821039B2 Layout architecture for improving circuit performance 有权
标题翻译：用于提高电路性能的布局架构
公开(公告)号：US07821039B2
公开(公告)日：2010-10-26
申请号：US12193354
申请日：2008-08-18
申请人： Li-Chun Tien , Lee-Chung Lu , Yung-Chin Hou , Chun-Hui Tai , Ta-Pen Guo , Sheng-Hsin Chen , Ping Chung Li
发明人： Li-Chun Tien , Lee-Chung Lu , Yung-Chin Hou , Chun-Hui Tai , Ta-Pen Guo , Sheng-Hsin Chen , Ping Chung Li
IPC分类号： H01L27/10 , H01L23/62 , H01L29/76 , H01L29/94 , H01L29/00
CPC分类号： H01L27/092 , H01L27/0207
摘要： An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight.
摘要翻译：集成电路结构包括集成电路结构，其包括：包括第一栅电极的PMOS晶体管; 第一源区; 和第一漏区; 包括第二栅电极的NMOS晶体管，其中所述第一栅电极和所述第二栅电极是栅电极条的部分; 第二源区; 和第二漏区。在PMOS晶体管和NMOS晶体管之间不会形成附加的晶体管。集成电路还包括连接到第一源极区的VDD电源轨; 连接到第二源区的VSS电力轨; 以及电连接到栅电极条的互连端口。互连端口位于包括PMOS晶体管，NMOS晶体管以及PMOS晶体管和NMOS晶体管之间的区域的MOS对区域的外侧。 MOS对区域中的栅电极条的部分基本上是直的。

43. 发明申请

US20100196803A1 Methods for Cell Boundary Isolation in Double Patterning Design 有权
标题翻译：双重图案设计中细胞边界隔离的方法
公开(公告)号：US20100196803A1
公开(公告)日：2010-08-05
申请号：US12616970
申请日：2009-11-12
申请人： Lee-Chung Lu , Yi-Kan Cheng , Yuan-Te Hou , Yung-Chin Hou , Li-Chun Tien
发明人： Lee-Chung Lu , Yi-Kan Cheng , Yuan-Te Hou , Yung-Chin Hou , Li-Chun Tien
IPC分类号： G03F1/00 , G06F17/50
CPC分类号： G03F1/70 , G03F1/00
摘要： A method of designing a double patterning mask set for a layout of a chip includes designing standard cells. In each of the standard cells, all left-boundary patterns are assigned with one of a first indicator and a second indicator, and all right-boundary patterns are assigned with an additional one of the first indicator and the second indicator. The method further includes placing the standard cells in a row of the layout of the chip. Starting from one of the standard cells in the row, indicator changes to the standard cells are propagated throughout the row. All patterns in the standard cells having the first indicator are transferred to a first mask of the double patterning mask set. All patterns in the standard cells having the second indicator are transferred to a second mask of the double patterning mask set.
摘要翻译：设计用于芯片布局的双重图案掩模组的方法包括设计标准单元。在每个标准单元中，所有左边界图案被分配有第一指示符和第二指示符中的一个，并且所有右边图案都被分配有第一指示符和第二指示符中的另外一个。该方法还包括将标准单元放置在芯片布局的一行中。从行中的一个标准单元开始，标记单元的指示符更改在整行中传播。具有第一指示符的标准单元中的所有图案被转移到双图案掩模组的第一掩模。具有第二指示器的标准单元中的所有图案被转移到双重图案掩模组的第二掩模。

44. 发明申请

US20090315079A1 Layout Architecture for Improving Circuit Performance 有权
标题翻译：用于提高电路性能的布局架构
公开(公告)号：US20090315079A1
公开(公告)日：2009-12-24
申请号：US12193354
申请日：2008-08-18
申请人： Li-Chun Tien , Lee-Chung Lu , Yung-Chin Hou , Chun-Hui Tai , Ta-Pen Guo , Sheng-Hsin Chen , Ping Chung Li
发明人： Li-Chun Tien , Lee-Chung Lu , Yung-Chin Hou , Chun-Hui Tai , Ta-Pen Guo , Sheng-Hsin Chen , Ping Chung Li
IPC分类号： H01L21/8238
CPC分类号： H01L27/092 , H01L27/0207
摘要： An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight.
摘要翻译：集成电路结构包括集成电路结构，其包括：包括第一栅电极的PMOS晶体管; 第一源区; 和第一漏区; 包括第二栅电极的NMOS晶体管，其中所述第一栅电极和所述第二栅电极是栅电极条的部分; 第二源区; 和第二漏区。在PMOS晶体管和NMOS晶体管之间不会形成附加的晶体管。集成电路还包括连接到第一源极区的VDD电源轨; 连接到第二源区的VSS电力轨; 以及电连接到栅电极条的互连端口。互连端口位于包括PMOS晶体管，NMOS晶体管以及PMOS晶体管和NMOS晶体管之间的区域的MOS对区域的外侧。 MOS对区域中的栅电极条的部分基本上是直的。

45. 发明授权

US07091614B2 Integrated circuit design for routing an electrical connection 有权
公开(公告)号：US07091614B2
公开(公告)日：2006-08-15
申请号：US10982634
申请日：2004-11-05
申请人： Chia-Lin Cheng , Ding-Dar Hu , Lee-Chung Lu
发明人： Chia-Lin Cheng , Ding-Dar Hu , Lee-Chung Lu
IPC分类号： H01L23/48 , H01L27/10
CPC分类号： H01L27/0203 , H01L23/525 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit for routing of an electrical connection include a first metal layer having a first set of dummy conductive segments discretely arranged, and a second metal layer having a second set of dummy conductive segments discretely arranged. The segments of the first and second sets are interleaved with vertically overlapped areas for providing a predetermined link path between a selected first and a selected second nodes on two dummy conductive segments by selectively connecting a predetermined subset of the first and second dummy conductive segments through their vertically overlapped areas.

46. 发明申请

US20060097395A1 Integrated circuit design for routing an electrical connection 有权
标题翻译：用于布线电气连接的集成电路设计
公开(公告)号：US20060097395A1
公开(公告)日：2006-05-11
申请号：US10982634
申请日：2004-11-05
申请人： Chia-Lin Cheng , Ding-Dar Hu , Lee-Chung Lu
发明人： Chia-Lin Cheng , Ding-Dar Hu , Lee-Chung Lu
IPC分类号： H01L27/10 , H01L21/4763
CPC分类号： H01L27/0203 , H01L23/525 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit for routing of an electrical connection include a first metal layer having a first set of dummy conductive segments discretely arranged, and a second metal layer having a second set of dummy conductive segments discretely arranged. The segments of the first and second sets are interleaved with vertically overlapped areas for providing a predetermined link path between a selected first and a selected second nodes on two dummy conductive segments by selectively connecting a predetermined subset of the first and second dummy conductive segments through their vertically overlapped areas.
摘要翻译：用于布线电连接的集成电路包括具有离散布置的第一组虚设导电段的第一金属层和具有离散布置的第二组虚设导电段的第二金属层。第一组和第二组的片段与垂直重叠的区域交错，用于通过选择性地连接第一和第二虚拟导电片段的预定子集，通过它们的两个虚拟导电片段，在两个虚拟导电片段上的选定的第一和第二节点之间提供预定的链接路径垂直重叠的区域。

47. 发明授权

US07640520B2 Design flow for shrinking circuits having non-shrinkable IP layout 有权
标题翻译：具有不可收缩IP布局的收缩电路的设计流程
公开(公告)号：US07640520B2
公开(公告)日：2009-12-29
申请号：US11807640
申请日：2007-05-30
申请人： Chung-Hsing Wang , Lee-Chung Lu , Cliff Hou , Lie-Szu Juang
发明人： Chung-Hsing Wang , Lee-Chung Lu , Cliff Hou , Lie-Szu Juang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： A method for processing an integrated circuit is provided. The method includes providing a first integrated circuit having a first scale, wherein the first integrated circuit comprises a shrinkable circuit comprising a first intellectual property (IP) layout, and a non-shrinkable circuit comprising a second IP layout; and generating a second integrated circuit having a second scale smaller than the first scale. The step of generating the second integrated circuit includes shrinking the shrinkable integrated circuit to the second scale. The method further includes merging the second IP layout with the non-shrinkable circuit to generate a final integrated circuit.
摘要翻译：提供了一种用于处理集成电路的方法。该方法包括提供具有第一标度的第一集成电路，其中第一集成电路包括包含第一知识产权（IP）布局的可收缩电路和包括第二IP布局的不可收缩电路; 以及生成具有小于所述第一刻度的第二刻度的第二集成电路。产生第二集成电路的步骤包括将可收缩集成电路收缩到第二刻度。该方法还包括将第二IP布局与不可收缩电路合并以产生最终集成电路。

48. 发明申请

US20080270813A1 Mother/daughter switch design with self power-up control 有权
标题翻译：母/子开关设计具有自上电控制功能
公开(公告)号：US20080270813A1
公开(公告)日：2008-10-30
申请号：US11789721
申请日：2007-04-24
申请人： Shih-Hsien Yang , Chung-Hsing Wang , Lee-Chung Lu , Chun-Hui Tai , Cliff Hou
发明人： Shih-Hsien Yang , Chung-Hsing Wang , Lee-Chung Lu , Chun-Hui Tai , Cliff Hou
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： System and method for providing power to integrated circuitry with good power-on responsive time and reduced power-on transient glitches. A preferred embodiment comprises a daughter switch coupled to a circuit block, a first control circuit coupled to the daughter circuit, a second control circuit coupled to the first control circuit, and a mother circuit coupled to the circuit block and to the second control circuit. After the daughter switch is turned on by a control signal, the mother switch is not turned on until the daughter switch has discharged (charged) the voltage potential across power rails of the mother circuit to a point where glitches are minimized. The second control circuit turns on the mother circuit when the reduced voltage potential is reached, with a signal produced by the first control circuit reflects the voltage potential. Furthermore, a bypass circuit can be used to reduce leakage current.
摘要翻译：为集成电路提供电源的系统和方法具有良好的上电响应时间和减少的上电瞬态毛刺。优选实施例包括耦合到电路块的子开关，耦合到子电路的第一控制电路，耦合到第一控制电路的第二控制电路以及耦合到电路块和第二控制电路的母电路。在通过控制信号接通子开关之后，母开关直到子开关已经将母电路的电源轨上的电压放电（充电）到毛刺最小化的位置为止。当达到降低的电压电位时，第二控制电路接通母电路，由第一控制电路产生的信号反映电压电位。此外，可以使用旁路电路来减少泄漏电流。

49. 发明授权

US07281230B2 Method of using mixed multi-Vt devices in a cell-based design 有权
标题翻译：在基于单元的设计中使用混合多Vt设备的方法
公开(公告)号：US07281230B2
公开(公告)日：2007-10-09
申请号：US11111281
申请日：2005-04-20
申请人： Shine Chien Chung , Cliff Hou , Kun-Lung Chen , Lee-Chung Lu
发明人： Shine Chien Chung , Cliff Hou , Kun-Lung Chen , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method is disclosed for utilizing mixed low threshold voltage (low-Vt) and high threshold voltage (high-Vt) devices in a cell-based design such that a tradeoff of both the circuit speed and power performance may be achieved. Using cells having non-uniform threshold devices for designing circuit, the speed or/and power optimization is comparable to fully custom designs.
摘要翻译：公开了一种在基于单元的设计中利用混合的低阈值电压（低Vt）和高阈值电压（高Vt）装置的方法，从而可以实现电路速度和功率性能的折衷。使用具有不均匀阈值器件的电池来设计电路，速度或/和功率优化与完全定制的设计相当。

50. 发明授权

US07797646B2 Method for using mixed multi-Vt devices in a cell-based design 有权
标题翻译：在基于单元的设计中使用混合多Vt设备的方法
公开(公告)号：US07797646B2
公开(公告)日：2010-09-14
申请号：US11844698
申请日：2007-08-24
申请人： Shine Chien Chung , Cliff Hou , Kun-Lung Chen , Lee-Chung Lu
发明人： Shine Chien Chung , Cliff Hou , Kun-Lung Chen , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method is disclosed for utilizing mixed low threshold voltage (low-Vt) and high threshold voltage (high-Vt) devices in a cell-based design such that a tradeoff of both the circuit speed and power performance may be achieved. Using cells having non-uniform threshold devices for designing circuit, the speed or/and power optimization is comparable to fully custom designs.
摘要翻译：公开了一种在基于单元的设计中利用混合的低阈值电压（低Vt）和高阈值电压（高Vt）装置的方法，从而可以实现电路速度和功率性能的折衷。使用具有不均匀阈值器件的电池来设计电路，速度或/和功率优化与完全定制的设计相当。

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