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41. 发明授权

US5687356A Hub and interface for isochronous token ring 失效
标题翻译：集线器和等时令牌环的接口
公开(公告)号：US5687356A
公开(公告)日：1997-11-11
申请号：US579555
申请日：1995-12-27
申请人： Claude Basso , Jean Calvignac , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Fabrice Verplanken
IPC分类号： G06F13/00 , H04L7/00 , H04L12/433 , H04L12/64 , G06F9/00
CPC分类号： H04L12/6418 , H04L12/433 , H04L2012/6437 , H04L2012/6451 , H04L2012/6454 , H04L2012/6459
摘要： A hub featuring ports for attachment of stations to a LAN comprises concentration logic (14) for the handling of multiplexed incoming and outgoing Token-Ring and isochronous signal streams. The concentration logic comprises clock recovery logic (42) from incoming Token-Ring packet data stream (40), for regeneration of Differential Manchester encoded data on output (400), and recovering of Token-Ring clock (401). A cycle framing generator (43) receives a 125 us synchronization clock from the hub backplane (402), and the Token-Ring clock (401), and generates control signals (403) to each of the 10 ports. Each port is comprised of a port transmit interface (44), and a port receive interface (45). Data from a connected station is input (404) to port receive interface (45). Token-Ring packet Differential Manchester encoded data are output (406) to the next active port, specifically to its port transmit interface, along with a recovered strobe clock (405), while ISO data are output (407) to switch (46). The switch and other concentration logic receive a hub local clock (412). Isochronous traffic interchanges with the hub backplane through leads 410 and 411; between ports or between ports and the hub through leads 407 and 409. Data to a connected station is output (408) from port transmit interface (44). Differential Manchester encoded data are received (400) along with Token-Ring clock (401). Control signals are input (403). Isochronous data are received (409). Token-Ring packet Differential Manchester encoded data are finally output from the concentration logic (41).
摘要翻译：具有用于将站附接到LAN的端口的集线器包括用于处理复用的进入和输出令牌环和等时信号流的集中逻辑（14）。浓度逻辑包括来自输入令牌环分组数据流（40）的时钟恢复逻辑（42），用于在输出（400）上再生差分曼彻斯特编码数据，以及恢复令牌环时钟（401）。周期成帧发生器（43）从集线器背板（402）和令牌环时钟（401）接收125 us同步时钟，并产生到10个端口中的每一个的控制信号（403）。每个端口由端口传输接口（44）和端口接收接口（45）组成。来自连接站的数据被输入（404）到端口接收接口（45）。令牌环包差分曼彻斯特编码数据输出（406）到下一个有效端口，特别是与其恢复的选通时钟（405）一起输出到其端口传输接口，同时将ISO数据输出（407）转换为开关（46）。交换机和其他集中逻辑接收集线器本地时钟（412）。通过引线410和411与轮毂底板进行同步通信交换; 通过引线407和409在端口之间或端口之间以及集线器之间。从端口传输接口（44）输出到连接站的数据（408）。接收差分曼彻斯特编码数据（400）以及令牌环时钟（401）。控制信号被输入（403）。接收同步数据（409）。令牌环包差分曼彻斯特编码数据最终从浓度逻辑输出（41）。

42. 发明授权

US08681819B2 Programmable multifield parser packet 失效
标题翻译：可编程多字段解析器包
公开(公告)号：US08681819B2
公开(公告)日：2014-03-25
申请号：US13017963
申请日：2011-01-31
申请人： Francois Abel , Jean Calvignac , Christoph Hagleitner , Jan van Lunteren , Fabrice Verplanken
发明人： Francois Abel , Jean Calvignac , Christoph Hagleitner , Jan van Lunteren , Fabrice Verplanken
IPC分类号： G01R31/08 , H04J3/24
CPC分类号： H04L69/22
摘要： A method of operating a packet parser in a computing system includes providing a configurable packet pointer by the packet parser, the packet pointer configured to index a configurable number of atomic parsing elements, the atomic parsing elements having a configurable size, in a data stream received by the computing system for extraction, wherein the indexed atomic parsing elements are non-contiguous in the data stream; and receiving the extracted indexed atomic parsing elements from the data stream by the packet parser.
摘要翻译：一种在计算系统中操作分组解析器的方法包括：由分组解析器提供可配置的分组指针，所述分组指针被配置为在接收的数据流中索引可配置数量的原子解析元素（所述原子解析元素具有可配置大小）由所述计算系统提取，其中所述索引的原子解析元素在所述数据流中不连续; 以及由分组解析器从数据流接收提取的索引原子解析元素。

43. 发明申请

US20050022196A1 Controller for multiple instruction thread processors 失效
标题翻译：多指令线程处理器的控制器
公开(公告)号：US20050022196A1
公开(公告)日：2005-01-27
申请号：US10915983
申请日：2004-08-11
申请人： Gordon Davis , Marco Heddes , Ross Leavens , Fabrice Verplanken
发明人： Gordon Davis , Marco Heddes , Ross Leavens , Fabrice Verplanken
IPC分类号： G06F9/46 , G06F9/38 , G06F9/48 , G06F9/52 , G06F15/16
CPC分类号： G06F9/3802 , G06F9/3851
摘要： A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.
摘要翻译：机制控制多线程处理器，使得当第一线程遇到第一预定义时间间隔的等待时间事件时，临时控制在第一预定义时间间隔的持续时间内被传送到备用执行线程，然后返回到原始线程。当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。

44. 发明授权

US6144637A Data communications 失效
标题翻译：数据通信
公开(公告)号：US6144637A
公开(公告)日：2000-11-07
申请号：US991911
申请日：1997-12-16
申请人： Jean Calvignac , Fabrice Verplanken , Daniel Orsatti
发明人： Jean Calvignac , Fabrice Verplanken , Daniel Orsatti
IPC分类号： H04L12/70 , H04Q11/04 , H04J3/14
CPC分类号： H04Q11/0478 , H04L2012/568
摘要： Traffic shaping apparatus is described for packet data communications networks, such as Asynchronous Transfer Mode (ATM) networks. The apparatus includes one or more packet queues for traffic having a plurality of different desired packet transfer rates, each queue being assigned to a connection having a predetermined desired packet transfer rate. Each incoming data packet is directed to the appropriate queue. Each of a plurality of timing circuits operate at a different frequency in a series of frequencies. The frequencies are selected so that the desired packet transfer rate for a connection can be established by summing outputs from more than one of the timing circuits.
摘要翻译：描述了用于分组数据通信网络（诸如异步传输模式（ATM））网络的流量整形装置。该装置包括用于具有多个不同期望分组传输速率的业务的一个或多个分组队列，每个队列被分配给具有预定的期望分组传送速率的连接。每个传入的数据包被引导到适当的队列。多个定时电路中的每一个在一系列频率中以不同的频率工作。选择频率使得可以通过对来自多于一个定时电路的输出求和来建立连接的期望分组传送速率。

45. 发明申请

US20120198213A1 PACKET HANDLER INCLUDING PLURALITY OF PARALLEL ACTION MACHINES 审中-公开
标题翻译：包装处理器，包括平行动作机械的多样性
公开(公告)号：US20120198213A1
公开(公告)日：2012-08-02
申请号：US13017949
申请日：2011-01-31
申请人： Francois Abel , Jean Calvignac , Christoph Hagleitner , Fabrice Verplanken
发明人： Francois Abel , Jean Calvignac , Christoph Hagleitner , Fabrice Verplanken
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/3016 , G06F9/3889
摘要： A packet handler for a packet processing system includes a plurality of parallel action machines, each of the plurality of parallel action machines being configured to perform a respective packet processing function; and a plurality of action machine input registers, wherein each of the plurality of parallel action machines is associated with one or more of the plurality of action machine input registers, and wherein an action machine of the plurality of parallel action machines is automatically triggered to perform its respective packet processing function in the event that data sufficient to perform the actions machine's respective packet processing function is written into the action machine's one or more respective action machine input registers.
摘要翻译：用于分组处理系统的分组处理器包括多个并行动作机器，所述多个并行动作机器中的每一个被配置为执行相应的分组处理功能; 以及多个动作机械输入寄存器，其中，所述多个并行动作机器中的每一个与所述多个动作机械输入寄存器中的一个或多个相关联，并且其中，所述多个并行动作机器的动作机器被自动触发以执行在足以执行动作机器相应的分组处理功能的数据被写入动作机器的一个或多个相应动作机器输入寄存器的情况下，其各自的分组处理功能。

46. 发明授权

US5768273A Method and apparatus for priority level queueing in processing ATM cell header and payload 失效
标题翻译：处理ATM信元头和有效载荷的优先级排队的方法和装置
公开(公告)号：US5768273A
公开(公告)日：1998-06-16
申请号：US547828
申请日：1995-11-01
申请人： Ange Aznar , Jean Calvignac , Daniel Orsatti , Dominique Rigal , Fabrice Verplanken
发明人： Ange Aznar , Jean Calvignac , Daniel Orsatti , Dominique Rigal , Fabrice Verplanken
IPC分类号： H04L12/931 , H04L12/935 , H04J3/22
CPC分类号： H04L49/30 , H04L49/205 , H04L49/3009
摘要： An ATM switch includes one or more adapters having input ports and/or output ports and a switching fabric for switching Asynchronous Transfer Mode (ATM) cells received at the input ports to the output ports. To maintain switch throughput, cells are categorized either as real time (high priority) or non-real time (lower priority) cells. High priority cells are processed using a first set of cell processing logic at a rate at least equal to the rate at which the cells are received on the input ports. Lower priority cells are processed using a second set of cell processing logic only when no high priority cells are being processed.
摘要翻译： ATM交换机包括具有输入端口和/或输出端口的一个或多个适配器，以及用于将在输入端口处接收的异步传输模式（ATM）单元切换到输出端口的交换结构。为了保持交换机吞吐量，小区被分类为实时（高优先级）或非实时（较低优先级）小区。使用第一组信元处理逻辑以至少等于在输入端口上接收信元的速率的速率处理高优先级信元。仅当不处理高优先级单元时，才使用第二组单元处理逻辑来处理低优先级单元。

47. 发明授权

US5684797A ATM cell multicasting method and apparatus 失效
标题翻译： ATM信元多播方法及装置
公开(公告)号：US5684797A
公开(公告)日：1997-11-04
申请号：US548030
申请日：1995-10-25
申请人： Ange Aznar , Jean Calvignac , Daniel Orsatti , Dominique Rigal , Fabrice Verplanken
发明人： Ange Aznar , Jean Calvignac , Daniel Orsatti , Dominique Rigal , Fabrice Verplanken
IPC分类号： H04L12/18 , H04L12/931 , H04L12/935 , H04L12/56
CPC分类号： H04L49/201 , H04L49/30
摘要： A multicasting apparatus and method for an Asynchronous Transfer Mode (ATM) switch is described, which uses a single target port (TP) vector attached to each outgoing ATM cell. The target port vector contains identifiers of each port to which the cell has to be transmitted. After transmission of the cell, the identifier relating to respective target port is erased from the TP vector. Hence the TP vector contains only identifiers of target port to which the cell has not yet been transmitted. When the TP vector contains no identifiers, the storage location at which the ATM cell is stored during the transmission, is freed for another cell. Unicast and multicast traffic are treated identically.
摘要翻译：描述了用于异步传输模式（ATM）交换机的多播设备和方法，其使用附接到每个输出ATM信元的单个目标端口（TP）向量。目标端口向量包含单元必须发送到的每个端口的标识符。在小区的传输之后，从TP向量中删除与各目标端口有关的标识符。因此，TP向量仅包含小区尚未被发送到的目标端口的标识符。当TP向量不包含标识符时，传输期间存储ATM信元的存储位置被释放用于另一小区。单播和多播流量处理相同。

48. 发明授权

US5557266A System for cascading data switches in a communication node 失效
标题翻译：用于在通信节点中级联数据交换机的系统
公开(公告)号：US5557266A
公开(公告)日：1996-09-17
申请号：US206363
申请日：1994-03-07
申请人： Jean Calvignac , Pierre Huon , Daniel Orsatti , Gilles Toubol , Fabrice Verplanken
发明人： Jean Calvignac , Pierre Huon , Daniel Orsatti , Gilles Toubol , Fabrice Verplanken
IPC分类号： H04L12/933 , H04L12/935 , H04L12/937 , H04L29/00 , H03K17/00
CPC分类号： H04L49/15 , H04L29/00 , H04L49/103 , H04L49/254 , H04L49/3027
摘要： A system for cascading data switches in a communication node allows for transfer of data among a plurality of adapters (30-i), expanding a moderate low cost switch 31-1 with additional hardware (31-2, 31-3, 31-4) to interconnect more adapters. The data transfers are performed by a plurality of Burst Relaying Cascaders (32-i) which connect the plurality of switches (31-i). A similar interface connect each adapter to the switch. A set of address information is used by the system to route the data from the source adapter to the target adapter, allowing navigation among the intermediate switches. Each interface contains a table where the address of every adapter of the whole system could be constructed dynamically at each communication node configuration.
摘要翻译：用于在通信节点中级联数据交换的系统允许在多个适配器（30-i）之间传输数据，用附加硬件（31-2,31-3-3,34-4）扩展适度的低成本开关31-1 ）来互连更多适配器。数据传送由连接多个开关（31-i）的多个突发中继级联（32-i）执行。类似的接口将每个适配器连接到交换机。系统使用一组地址信息将数据从源适配器路由到目标适配器，允许在中间交换机之间导航。每个接口包含一个表，其中可以在每个通信节点配置下动态构建整个系统的每个适配器的地址。

49. 发明申请

US20070294471A1 DRAM ACCESS COMMAND QUEUING METHOD 有权
标题翻译： DRAM访问命令队列方法
公开(公告)号：US20070294471A1
公开(公告)日：2007-12-20
申请号：US11832220
申请日：2007-08-01
申请人： Jean Calvignac , Chih-jen Chang , Gordon Davis , Fabrice Verplanken
发明人： Jean Calvignac , Chih-jen Chang , Gordon Davis , Fabrice Verplanken
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.
摘要翻译：访问仲裁器被用于将对DRAM存储器件，特别是快速循环DRAM中的各个存储体的读取和写入访问请求进行优先级排序。这用于通过避免对同一存储体的连续访问并且通过最小化死循环来优化用于读取和写入操作的存储器带宽。仲裁器首先将DRAM访问划分为写访问和读访问。访问请求被划分为每个存储体的访问，并且对每个存储体的访问次数施加了阈值限制。基于写入队列状态，写入接收数据包在存储体之间旋转。每个存储体的写入队列的状态也可以用于系统流控制。仲裁器还通常包括基于命令队列的状态来确定访问窗口的能力，并且在每个访问窗口上执行仲裁。

50. 发明申请

US20060285551A1 STM-1 TO STM-64 SDH/SONET FRAMER WITH DATA MULTIPLEXING FROM A SERIES OF CONFIGURABLE I/O PORTS 有权
标题翻译： STM-1到STM-64 SDH / SONET框架，具有从一系列可配置I / O端口进行数据多路复用
公开(公告)号：US20060285551A1
公开(公告)日：2006-12-21
申请号：US11467848
申请日：2006-08-28
申请人： Kenneth Barker , Rolf Clauberg , Jean Calvignac , Andreas Herkersdorf , Fabrice Verplanken , David Webb
发明人： Kenneth Barker , Rolf Clauberg , Jean Calvignac , Andreas Herkersdorf , Fabrice Verplanken , David Webb
IPC分类号： H04J3/22
CPC分类号： H04J3/1611 , H04J3/0685 , H04J3/22 , H04J2203/0089
摘要： The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port snning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.
摘要翻译：本发明涉及一种用于将具有输入数据速率的至少两个数据信号组合成具有高于用于在共享介质上传输的输入数据速率的输出数据速率的单个数据流的装置，反之亦然，特别涉及一种单个SDH / SONET成帧器能够处理从STM-i到STM-j的大范围的SDH / SONET帧，具有对应于STM-j帧的聚合总容量，其中i和j是从1到64的整数或根据SDH / SONET标准的STM-N定义更高。更进一步地，本发明也可以扩展到使用STS-1作为最低范围。 STS-1仅存在于SONET中而不是SDH，对应于156Mb / s的STM-1的三分之一的51.5Mb / s的数据速率。根据本发明的装置包括用于接收和/或发送所述至少两个数据信号的至少两个端口，用于从由所述端口接收的数据信号中提取数据和/或合成要通过所述端口发送的数据的端口捕捉单元其中所述端口扫描单元被配置为从提供具有至少两个不同输入数据速率的数据流的端口提取数据和/或合成要通过端口发送的数据，该数据流具有至少两个不同数据速率的数据流。

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