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41. 发明申请

US20070073942A1 High-speed interface circuit for semiconductor memory chips and memory system including the same 有权
标题翻译：用于半导体存储器芯片的高速接口电路和包含相同的存储器系统
公开(公告)号：US20070073942A1
公开(公告)日：2007-03-29
申请号：US11226457
申请日：2005-09-15
申请人： Peter Gregorius , Hermann Ruckerbauer , Paul Wallner
发明人： Peter Gregorius , Hermann Ruckerbauer , Paul Wallner
IPC分类号： G06F13/38
CPC分类号： G11C7/1006 , G11C2207/107 , H03M9/00
摘要： In a semiconductor memory system, the memory chips are linked to a memory module in a shared loop forward architecture and connected in a point-to-point connection to a memory controller. Each memory chip includes a high-speed interface circuit including: a read and write data/command-and-address signal re-driver/transmitter path for re-driving serial read data and write data/command-and-address signals not destined for the semiconductor memory chip; and a main signal path which includes a serial-to-parallel converter and a synchronizer for serial-to-parallel converting and synchronizing with a reference clock signal write data/command-and-address signals destined for the semiconductor memory chip as well as a parallel-to-serial converter for parallel-to-serial converting read data signals read from a memory core of the memory chips, and a switch for inserting the parallel-to-serial converted read data signals into the re-driver/transmitter path. Optionally the high-speed interface circuit additionally includes a transparent re-driver/transmitter path not including any synchronizing circuitry.
摘要翻译：在半导体存储器系统中，存储器芯片被链接到共享回路前向架构中的存储器模块，并且以点对点连接连接到存储器控制器。每个存储器芯片包括一个高速接口电路，包括：用于重新驱动串行读取数据的读取和写入数据/命令和地址信号重新驱动器/发送器路径，并且写入不预定的数据/命令和地址信号半导体存储芯片; 以及主信号路径，其包括串行到并行转换器和用于串行到并行转换并与参考时钟信号同步的同步器，写入用于半导体存储器芯片的数据/命令和地址信号以及一个并行到串行转换器，用于并行到串行转换从存储器芯片的存储器核心读取的读取数据信号，以及用于将并行到串行转换的读取数据信号插入重新驱动器/发送器路径的开关。可选地，高速接口电路还包括不包括任何同步电路的透明重新驱动器/发射器路径。

42. 发明授权

US07414917B2 Re-driving CAwD and rD signal lines 失效
标题翻译：重新启动CAwD和rD信号线
公开(公告)号：US07414917B2
公开(公告)日：2008-08-19
申请号：US11192335
申请日：2005-07-29
申请人： Hermann Ruckerbauer , Simon Muff , Christian Weiss , Peter Gregorius
发明人： Hermann Ruckerbauer , Simon Muff , Christian Weiss , Peter Gregorius
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G11C5/06 , H05K1/142
摘要： Semiconductor memory modules and semiconductor memory systems using the same are described herein. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input lines and the rD signal output lines in a respective point-to-point fashion.
摘要翻译：本文描述了使用其的半导体存储器模块和半导体存储器系统。这些模块将常规DIMM分成一系列独立的较小内存模块。每个存储器模块包括布置在衬底上的至少一个半导体存储器芯片; CAwD信号输入线，以第一预定行号排列在基板上，并将半导体存储器芯片之一连接到基板上的CAwD输入信号引脚; 和rD信号输出线，以第二预定行号排列在基板上，并将一个或最后一个半导体存储器连接到基板的第二数量的rD输出信号引脚。在包括半导体存储器模块的半导体存储器系统中，每个存储器模块通过CAwD信号输入线和rD信号输出线分别以点对点的方式连接到存储器控制器。

43. 发明授权

US07180821B2 Memory device, memory controller and memory system having bidirectional clock lines 有权
标题翻译：存储器件，存储器控制器和具有双向时钟线的存储器系统
公开(公告)号：US07180821B2
公开(公告)日：2007-02-20
申请号：US10954869
申请日：2004-09-30
申请人： Hermann Ruckerbauer , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C5/04 , G11C7/22 , G11C7/225
摘要： One embodiment of the present invention provides to a memory device adapted to receive data according to a write clock signal and to output data according to a read clock signal, comprising a clock port configured to output the read clock signal and to receive the write clock signal and a serial bidirectional driver configured to output the read clock signal via the clock port and to receive the write clock signal via the clock port simultaneously.
摘要翻译：本发明的一个实施例提供了一种适于根据写时钟信号接收数据并根据读时钟信号输出数据的存储器件，包括配置成输出读时钟信号并接收写时钟信号的时钟端口以及串行双向驱动器，被配置为经由时钟端口输出读取时钟信号，并经由时钟端口同时接收写时钟信号。

44. 发明申请

US20060112230A1 Integrated memory device and memory module 审中-公开
标题翻译：集成存储器件和存储器模块
公开(公告)号：US20060112230A1
公开(公告)日：2006-05-25
申请号：US10996956
申请日：2004-11-24
申请人： Christian Sichert , Hermann Ruckerbauer , Dominique Savignac , Peter Gregorius , Paul Wallner
发明人： Christian Sichert , Hermann Ruckerbauer , Dominique Savignac , Peter Gregorius , Paul Wallner
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F2212/6022
摘要： The present invention relates to an integrated memory device including: memory cells arranged at wordlines and bitlines, wherein the memory cells are addressable in sets of 2n bit, wherein n is an integer, a pre-fetch read unit to pre-fetch an addressed set of 2n data bit in parallel from the addressed memory area, buffer memory to buffer the number of pre-fetched data bits; a number m of output ports to output the data bits buffered in the buffer memory; an output controller for controlling the outputting of the data bits buffered in the buffer memory to the number m of output ports in groups of m bits in one or a plurality of successive cycles, characterized in that the number m of output ports is different to any of the possible numbers 2n of the sets of addressable memory cells.
摘要翻译：本发明涉及一种集成存储器件，其包括：以字线和位线布置的存储器单元，其中存储器单元可以以2位为单位的集合寻址，其中n是整数，预取读取单元，用于从寻址的存储器区域缓冲存储器并行地预取寻址的2 数据位组，以缓冲预取数据位的数量; 多个输出端口输出缓冲存储器中缓冲的数据位; 输出控制器，用于在一个或多个连续循环中控制以缓冲存储器缓冲的数据位输出到m位组的输出端口的数量m，其特征在于，输出端口的数量m不同于任何的可寻址存储器单元组的可能数字2 。

45. 发明申请

US20060067156A1 Memory device, memory controller and memory system having bidirectional clock lines 有权
标题翻译：具有双向时钟线的存储器件，存储器控制器和存储器系统
公开(公告)号：US20060067156A1
公开(公告)日：2006-03-30
申请号：US10954869
申请日：2004-09-30
申请人： Hermann Ruckerbauer , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C5/04 , G11C7/22 , G11C7/225
摘要： One embodiment of the present invention provides to a memory device adapted to receive data according to a write clock signal and to output data according to a read clock signal, comprising a clock port configured to output the read clock signal and to receive the write clock signal and a serial bidirectional driver configured to output the read clock signal via the clock port and to receive the write clock signal via the clock port simultaneously.
摘要翻译：本发明的一个实施例提供了一种适于根据写时钟信号接收数据并根据读时钟信号输出数据的存储器件，包括配置成输出读时钟信号并接收写时钟信号的时钟端口以及串行双向驱动器，被配置为经由时钟端口输出读取时钟信号，并经由时钟端口同时接收写时钟信号。

46. 发明申请

US20070195505A1 Memory module device 审中-公开
标题翻译：内存模块设备
公开(公告)号：US20070195505A1
公开(公告)日：2007-08-23
申请号：US11357413
申请日：2006-02-21
申请人： Dominique Savignac , Peter Gregorius , Hermann Ruckerbauer , Simon Muff
发明人： Dominique Savignac , Peter Gregorius , Hermann Ruckerbauer , Simon Muff
IPC分类号： H05K7/20
CPC分类号： H05K1/183 , G11C5/02 , G11C5/025 , G11C5/04 , H01L23/552 , H01L24/73 , H01L25/18 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2924/01019 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/16195 , H01L2924/16251 , H01L2924/19107 , H01L2924/3025 , H05K1/181 , H05K2201/10159 , H05K2201/10515 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A memory module device includes a printed circuit board, a plurality of memory modules and a buffer module. Lines are provided in or on the printed circuit board to connect the buffer module to the memory modules. The memory modules are combined at least partially to form memory module stacks.
摘要翻译：存储器模块装置包括印刷电路板，多个存储器模块和缓冲模块。在印刷电路板中或印刷电路板上提供线路，以将缓冲模块连接到存储器模块。存储器模块至少部分地组合以形成存储器模块堆栈。

47. 发明申请

US20070057695A1 Semiconductor memory chip with re-drive unit for electrical signals 审中-公开
标题翻译：半导体存储芯片，带有重新驱动单元的电信号
公开(公告)号：US20070057695A1
公开(公告)日：2007-03-15
申请号：US11226456
申请日：2005-09-15
申请人： Hermann Ruckerbauer , Peter Gregorius
发明人： Hermann Ruckerbauer , Peter Gregorius
IPC分类号： H03K19/0175
CPC分类号： G11C11/4096 , G06F13/4077 , G11C7/1066
摘要： A semiconductor memory chip includes a re-drive unit for re-driving electrical signals to at least one semiconductor memory chip connected thereto. The re-drive unit includes a direct line connection between two connecting nodes, i.e., one input terminal and one output terminal of the semiconductor memory chip.
摘要翻译：半导体存储器芯片包括用于将电信号重新驱动到连接到其上的至少一个半导体存储器芯片的重新驱动单元。重新驱动单元包括两个连接节点之间的直接线路连接，即半导体存储器芯片的一个输入端子和一个输出端子。

48. 发明申请

US20060123265A1 Semiconductor memory module 有权
标题翻译：半导体存储器模块
公开(公告)号：US20060123265A1
公开(公告)日：2006-06-08
申请号：US11002148
申请日：2004-12-03
申请人： Hermann Ruckerbauer , Abdallah Bacha , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Abdallah Bacha , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
IPC分类号： G06F1/04
CPC分类号： G11C5/04 , G11C5/063
摘要： A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.
摘要翻译：半导体存储器模块包括多个半导体存储器芯片和总线信号线，其向半导体存储器芯片提供输入时钟信号和输入命令和地址信号。时钟信号再生电路和寄存器电路以连接到总线信号线的公共芯片封装布置在半导体存储器模块中。时钟信号再生电路和寄存器电路分别对输入的时钟信号进行调节，并临时存储输入的命令和地址信号，分别将经调节的时钟信号和临时存储的命令和地址信号乘以1：X，分别提供对半导体存储器芯片调节时钟信号和临时存储的命令和地址信号。

49. 发明申请

US20060095826A1 Semiconductor memory chip, semiconductor memory module and method for transmitting write data to semiconductor memory chips 审中-公开
标题翻译：半导体存储器芯片，半导体存储器模块和用于将写数据发送到半导体存储器芯片的方法
公开(公告)号：US20060095826A1
公开(公告)日：2006-05-04
申请号：US11261911
申请日：2005-10-31
申请人： Hermann Ruckerbauer , Doninique Savignac , Peter Gregorius , Christian Sichert , Paul Wallner
发明人： Hermann Ruckerbauer , Doninique Savignac , Peter Gregorius , Christian Sichert , Paul Wallner
IPC分类号： H04L1/18 , G08C25/02
CPC分类号： G11C5/063 , G06F11/1044 , G11C7/10 , G11C11/4093
摘要： A semiconductor memory module includes a plurality of semiconductor memory chips. Each semiconductor memory chip includes an interface circuit that is configured to detect a transmission error in a write datum and is further configured to output, via a separate signal path, a repeat request signal for the repeated transmission of the write datum detected as erroneous. This repeat request signal can be transmitted either as a single-bit signal or as a multibit signal (e.g., serially as an individual signal line to a superordinate memory controller).
摘要翻译：半导体存储器模块包括多个半导体存储器芯片。每个半导体存储器芯片包括接口电路，其被配置为检测写入数据中的传输错误，并且还被配置为经由单独的信号路径输出用于重复发送被检测为错误的写入数据的重复请求信号。该重复请求信号可以作为单位信号或作为多位信号（例如，串行地作为单独的信号线发送到上级存储器控制器）来发送。

50. 发明申请

US20060067157A1 Memory system with two clock lines and a memory device 有权
标题翻译：具有两个时钟线和存储器件的存储器系统
公开(公告)号：US20060067157A1
公开(公告)日：2006-03-30
申请号：US10955177
申请日：2004-09-30
申请人： Hermann Ruckerbauer , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
IPC分类号： G11C8/00 , G11C5/06
CPC分类号： G11C5/04 , G11C5/063 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.
摘要翻译：本发明涉及一种具有两条时钟线的存储器件的存储器系统。本发明的一个实施例提供了一种存储器系统，其包括至少一个存储器件，用于控制存储器件的操作的存储器控制器，从存储器控制器的写时钟输出延伸到存储器的时钟端口的第一时钟线向存储器件提供时钟信号的第二时钟线，以及从存储器件的时钟端口延伸到存储器控制器的读时钟输入端的第二时钟线，以将施加到存储器件的时钟端口的时钟信号转发回到存储器控制器的读时钟输入。存储器件还可以包括同步电路，其适于从存储器控制器接收时钟信号，并提供与转发的时钟信号同步的输出数据。

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