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41. 发明申请

US20050145927A1 NON-VOLATILE MEMORY CELL 有权
公开(公告)号：US20050145927A1
公开(公告)日：2005-07-07
申请号：US10905056
申请日：2004-12-13
申请人： Ching-Hsiang Hsu , Shih-Jye Shen , Hsin-Ming Chen , Hai-Ming Lee
发明人： Ching-Hsiang Hsu , Shih-Jye Shen , Hsin-Ming Chen , Hai-Ming Lee
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/76
CPC分类号： G11C16/0433 , G11C16/0466 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/7923
摘要： A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is formed on the N-type well and between the first doped region and the second doped region from among the three P-type doped regions. The first gate is formed on the first stacked dielectric layer. The second stacked dielectric layer is formed on the N-type well and between the second doped region and the third doped region from among the three P-type doped regions. The second gate is formed on the second stacked dielectric layer.

42. 发明授权

US06882574B2 Single poly UV-erasable programmable read only memory 有权
标题翻译：单个聚UV可擦除可编程只读存储器
公开(公告)号：US06882574B2
公开(公告)日：2005-04-19
申请号：US10605235
申请日：2003-09-17
申请人： Ching-Sung Yang , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Ching-Sung Yang , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： G11C16/04
CPC分类号： G11C16/0408 , G11C16/0433 , G11C2216/10 , G11C2216/18 , H01L27/11521 , H01L27/11558
摘要： An erasable programmable read only memory includes two serially connected P-type metal-oxide semiconductor (MOS) transistors, wherein a first P-type MOS transistor acts as select transistor, a gate of the first P-type MOS transistor is coupled to select gate voltage, a first node of the first P-type MOS transistor connected to source line voltage, a second node of the first P-type MOS transistor connected to a first node of a second P-type MOS transistor, wherein a second node of the second P-type MOS transistor is connected to bit line voltage, wherein a gate of the second P-type MOS transistor serves as a floating gate, wherein the erasable programmable read only memory does not need to bias a certain voltage on a control gate for programming and thereby injecting hot carriers onto the floating gate, and wherein the erasable programmable read only memory is capped by dielectric materials which are transparent to ultraviolet (UV) light.
摘要翻译：可擦除可编程只读存储器包括两个串联的P型金属氧化物半导体（MOS）晶体管，其中第一P型MOS晶体管用作选择晶体管，第一P型MOS晶体管的栅极耦合到选择栅极电压，连接到源极线电压的第一P型MOS晶体管的第一节点，与第二P型MOS晶体管的第一节点连接的第一P型MOS晶体管的第二节点，其中，第二P型MOS晶体管连接到位线电压，其中第二P型MOS晶体管的栅极用作浮置栅极，其中可擦除可编程只读存储器不需要在控制栅极上偏置一定电压，编程，从而将热载体注入到浮动栅极上，并且其中可擦除可编程只读存储器被对紫外线（UV）光透明的电介质材料封盖。

43. 发明授权

US06750504B2 Low voltage single-poly flash memory cell and array 失效
标题翻译：低电压单聚光闪存单元和阵列
公开(公告)号：US06750504B2
公开(公告)日：2004-06-15
申请号：US10063444
申请日：2002-04-24
申请人： Ching-Sung Yang , Shih-Jye Shen , Wei-Zhe Wong , Ching-Hsiang Hsu
发明人： Ching-Sung Yang , Shih-Jye Shen , Wei-Zhe Wong , Ching-Hsiang Hsu
IPC分类号： H01L2972
CPC分类号： H01L29/792 , G11C16/0466 , H01L27/115
摘要： A low voltage single-poly flash memory cell includes a first ion well of a first conductivity type, a second ion well of a second conductivity type formed on the first ion well, a charge storage layer comprising a first insulating layer, a trapping layer, and a second insulating layer, located on the second ion well, a gate located on the charge storage layer, a sourceand a drain of the second conductivity type located in two sides of the charge storage layer, and an ion doped region of the first conductivity type formed in the second ion well and under and surrounding the source and at least a portion of a bottom of the first insulating layer.
摘要翻译：低电压单聚光闪存单元包括第一导电类型的第一离子阱，形成在第一离子阱上的第二导电类型的第二离子阱，电荷存储层，其包含第一绝缘层，俘获层，以及位于所述第二离子阱上的第二绝缘层，位于所述电荷存储层上的栅极，位于所述电荷存储层的两侧的所述第二导电类型的源极和漏极以及所述第一导电性的离子掺杂区域形成在所述第二离子阱中并且在所述源的下面和周围以及所述第一绝缘层的底部的至少一部分。

44. 发明授权

US06504763B1 Nonvolatile semiconductor memory capable of random programming 失效
标题翻译：非易失性半导体存储器，能够进行随机编程
公开(公告)号：US06504763B1
公开(公告)日：2003-01-07
申请号：US09683845
申请日：2002-02-21
申请人： Ching-Sung Yang , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Ching-Sung Yang , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/12 , H01L27/115 , H01L27/11524
摘要： A nonvolatile semiconductor memory capable of random programming has a semiconductor substrate of a first conductivity type having a memory region, a deep ion well of a second conductivity type located in the semiconductor substrate within the memory region, a shallow ion well of the first conductivity type isolated by an STI layer within the deep ion well, at least one NAND cell block located on the semiconductor substrate within the shallow ion well, and a bit line located over the semiconductor substrate used to provide a first predetermined voltage for the shallow ion well during a data program mode via a conductive plug which electrically connects to the bit line and extends downward to the shallow ion well. Consequently, during a programming operation, only a selected word line is required to have an appropriate voltage applied to it. Thus, the power needed is reduced and access time is shortened.
摘要翻译：能够进行随机编程的非易失性半导体存储器具有具有存储区域的第一导电类型的半导体衬底，位于存储区域内的半导体衬底中的第二导电类型的深离子阱，第一导电类型的浅离子阱通过深离子阱内的STI层隔离，位于浅离子阱内的半导体衬底上的至少一个NAND单元块，以及位于半导体衬底上方的位线，用于为浅离子阱提供第一预定电压通过电连接到位线并向下延伸到浅离子阱的导电插头的数据程序模式。因此，在编程操作期间，仅需要选择的字线来施加适当的电压。因此，所需的功率减少，并且访问时间缩短。

45. 发明申请

US20120276700A1 READ-ONLY MEMORY AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：只读存储器及其制造方法
公开(公告)号：US20120276700A1
公开(公告)日：2012-11-01
申请号：US13549525
申请日：2012-07-16
申请人： Ching-Hsiang Hsu , Ching-Sung Yang , Shih-Jye Shen
发明人： Ching-Hsiang Hsu , Ching-Sung Yang , Shih-Jye Shen
IPC分类号： H01L21/336
CPC分类号： H01L27/112 , G11C17/12 , H01L27/1126
摘要： A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.
摘要翻译：掩模定义的只读存储器阵列形成在衬底上，并且包括具有相反极性的第一ROM位和第二ROM位。第一ROM位具有形成在衬底的第一区域上的第一MOS晶体管和第一阻挡层。第一MOS晶体管的第二源极/漏极区域和第一扩散区域形成在第一块层的相对侧上的衬底的第一区域中。第二ROM位包括第二MOS晶体管。

46. 发明授权

US07960792B2 Non-volatile memory with a stable threshold voltage on SOI substrate 有权
标题翻译：在SOI衬底上具有稳定阈值电压的非易失性存储器
公开(公告)号：US07960792B2
公开(公告)日：2011-06-14
申请号：US12943945
申请日：2010-11-11
申请人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： H01L29/786 , H01L29/792
CPC分类号： H01L27/115
摘要： A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.
摘要翻译：设置在SOI衬底中的非易失性存储器。非易失性存储器包括存储单元和第一导电类型掺杂区域。存储单元包括栅极，电荷存储结构，底部电介质层，第二导电类型漏极区域和第二导电型源极区域。栅极设置在SOI衬底上。电荷存储结构设置在栅极和SOI衬底之间。底部电介质层设置在电荷存储层和SOI衬底之间。第二导电型漏极区域和第二导电型源极区域设置在栅极的两侧旁边的第一导电型硅体层中。第一导电型掺杂区域设置在第一导电型硅体层中，并且与栅极下方的第一导电型硅体层电连接。

47. 发明授权

US07682908B2 Non-volatile memory and operating method thereof 有权
标题翻译：非易失性存储器及其操作方法
公开(公告)号：US07682908B2
公开(公告)日：2010-03-23
申请号：US11163716
申请日：2005-10-28
申请人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： H01L21/336 , H01L27/088 , H01L27/108
CPC分类号： H01L29/792 , G11C16/0433 , G11C16/10 , H01L27/115
摘要： A non-volatile memory including a substrate, a first doped region, a second doped region, a third doped region, a first gate structure, and a second gate structure is disclosed. The doped regions are disposed in the substrate and the second doped region is disposed between the first doped region and the third doped region. The first gate structure is disposed on the substrate between the first doped region and the second doped region. The second gate structure is disposed on the substrate between the second doped region and the third doped region, and comprises a tunneling dielectric layer, a charge trapping structure and a gate from the bottom up.
摘要翻译：公开了包括衬底，第一掺杂区，第二掺杂区，第三掺杂区，第一栅极结构和第二栅极结构的非易失性存储器。掺杂区域设置在衬底中，第二掺杂区域设置在第一掺杂区域和第三掺杂区域之间。第一栅极结构设置在第一掺杂区和第二掺杂区之间的衬底上。第二栅极结构设置在第二掺杂区域和第三掺杂区域之间的衬底上，并且包括隧道电介质层，电荷捕获结构和从下向上的栅极。

48. 发明授权

US07417897B2 Method for reading a single-poly single-transistor non-volatile memory cell 有权
标题翻译：读取单多晶单晶体管非易失性存储单元的方法
公开(公告)号：US07417897B2
公开(公告)日：2008-08-26
申请号：US11625829
申请日：2007-01-23
申请人： Hsin-Ming Chen , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Hsin-Ming Chen , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： G11C11/34
CPC分类号： G11C17/16 , G11C2216/26
摘要： A method for operating a single-poly, single-transistor (1-T) non-volatile memory (NVM) cell. The NVM cell includes a gate on a P substrate, a gate dielectric layer, an N drain region and an N source region. N channel is defined between the N drain region and N source region. The NVM cell is programmed by breaking down the gate dielectric layer. To read the NVM cell, a positive voltage is provided to N drain region, a positive voltage is provided to the gate, and grounding the N source region and the P substrate.
摘要翻译：一种用于操作单晶体，单晶体管（1-T）非易失性存储器（NVM）单元的方法。 NVM单元包括在P基板上的栅极，栅极电介质层，N漏极区域和N源极区域。 N沟道定义在N漏极区域和N源极区域之间。 NVM单元通过分解栅极电介质层进行编程。为了读取NVM单元，向N漏极区域提供正电压，向栅极提供正电压，并将N源极区域和P基板接地。

49. 发明授权

US07250654B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US07250654B2
公开(公告)日：2007-07-31
申请号：US11163984
申请日：2005-11-07
申请人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A single-poly non-volatile memory device invented to integrate into logic process is disclosed. This non-volatile memory device includes a memory cell unit comprising a PMOS access transistor that is serially connected to a PMOS storage transistor formed in a cell array area, and, in a peripheral circuit area, a high-voltage MOS transistor having a high-voltage gate insulation layer is provided. The PMOS access transistor has an access gate oxide layer that has a thickness equal to the thickness of the high-voltage gate insulation layer in a peripheral circuit area.
摘要翻译：公开了发明用于集成到逻辑过程中的单一多重非易失性存储器件。该非易失性存储器件包括存储单元单元，该存储单元单元包括串联连接到形成在单元阵列区域中的PMOS存储晶体管的PMOS存取晶体管，并且在外围电路区域中具有高电压MOS晶体管，提供了电压栅极绝缘层。 PMOS存取晶体管具有与外围电路区域中的高压栅极绝缘层的厚度相等的栅极氧化层。

50. 发明授权

US07172940B1 Method of fabricating an embedded non-volatile memory device 有权
标题翻译：制造嵌入式非易失性存储器件的方法
公开(公告)号：US07172940B1
公开(公告)日：2007-02-06
申请号：US11162572
申请日：2005-09-15
申请人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： H01L21/8247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573 , H01L29/66833 , Y10S438/954
摘要： A method of fabricating a non-volatile memory based on SONOS is disclosed. By masking the peripheral circuit area with a reverse ONO photoresist layer, the residual ONO layer that is not covered by a gate within the memory array area is etched away to expose the substrate. After the etching of the ONO layer, a channel adjustment doping is carried out subsequently using the reverse ONO photoresist layer as an implant mask, thereby forming lightly doped regions next to the gate within the memory array area. Finally, the reverse ONO photoresist layer is then stripped.
摘要翻译：公开了一种制造基于SONOS的非易失性存储器的方法。通过用反向ONO光致抗蚀剂层掩蔽外围电路区域，蚀刻掉未被存储器阵列区域内的栅极覆盖的残余ONO层以露出衬底。在ONO层的蚀刻之后，随后使用反向ONO光致抗蚀剂层作为注入掩模进行沟道调节掺杂，从而在存储器阵列区域内形成栅极旁边的轻掺杂区域。最后，剥离反向ONO光致抗蚀剂层。

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