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41. 发明申请

US20100117231A1 RELIABLE WAFER-LEVEL CHIP-SCALE SOLDER BUMP STRUCTURE 审中-公开
标题翻译：可靠的水平切割尺寸焊接结构
公开(公告)号：US20100117231A1
公开(公告)日：2010-05-13
申请号：US12690179
申请日：2010-01-20
申请人： Dennis Lang , Sonbol Vaziri , James Kent Naylor , Eric Woolsey , Chung-Lin Wu , Mike Gruenhagen , Neill Thornton
发明人： Dennis Lang , Sonbol Vaziri , James Kent Naylor , Eric Woolsey , Chung-Lin Wu , Mike Gruenhagen , Neill Thornton
IPC分类号： H01L23/498
CPC分类号： H01L23/3114 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05022 , H01L2224/05557 , H01L2224/05558 , H01L2224/13022 , H01L2224/13023 , H01L2224/131 , H01L2224/16 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2224/13099
摘要： A wafer level chip scale package (WLCSP) includes a semiconductor device with a plurality of solder bump pads, patterned passivation regions above each of the solder bump pads, a patterned under bump metallization (UBM) region on each of the solder bump pads and the passivation regions, a polyimide region over a portion of the UBM regions and the passivation regions, solder bumps formed on each of the UBM regions.
摘要翻译：晶片级芯片级封装（WLCSP）包括具有多个焊料凸块焊盘的半导体器件，每个焊料凸块焊盘上方的图案化钝化区域，每个焊料凸块焊盘上的图案化凸点下金属化（UBM）区域，以及钝化区域，UBM区域的一部分上的聚酰亚胺区域和钝化区域，形成在每个UBM区域上的焊料凸块。

42. 发明申请

US20090166850A1 High-Power Semiconductor Die Packages With Integrated Heat-Sink Capability and Methods of Manufacturing the Same 有权
标题翻译：具有集成散热能力的大功率半导体芯片封装及其制造方法
公开(公告)号：US20090166850A1
公开(公告)日：2009-07-02
申请号：US11968602
申请日：2008-01-02
申请人： Oseob Jeon , Chung-Lin Wu , Eddy Tjhia , Bigildis C. Dosdos
发明人： Oseob Jeon , Chung-Lin Wu , Eddy Tjhia , Bigildis C. Dosdos
IPC分类号： H01L21/50 , H01L23/40
CPC分类号： H01L23/49816 , H01L23/3128 , H01L23/3675 , H01L23/40 , H01L23/49562 , H01L23/49805 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/73 , H01L25/072 , H01L25/16 , H01L2224/16 , H01L2224/371 , H01L2224/37147 , H01L2224/3754 , H01L2224/40095 , H01L2224/40225 , H01L2224/48091 , H01L2224/48247 , H01L2224/732 , H01L2224/73253 , H01L2224/73255 , H01L2224/73265 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/19042 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An exemplary semiconductor die package of the invention has a metal-oxide substrate disposed between a first surface of a semiconductor die and a heat-sinking component, with a conductive die clip or one or more electrical interconnect traces disposed between the metal-oxide substrate and the first surface of the semiconductor die. The heat-sinking component may comprise a heat sink, or an adaptor plate to which a heat sink may be coupled. The conductive die clip or electrical trace(s) provides electrical connection(s) to the first surface of the semiconductor die, while the metal-oxide substrate electrically insulates the die from the heat-sinking component, and provides a path of high thermal conductivity between the die and the heat-sinking component. The second surface of the semiconductor die may be left free to connect to a circuit board, or a leadframe or interconnect substrate may be attached to it.
摘要翻译：本发明的示例性半导体管芯封装具有设置在半导体管芯的第一表面和散热部件之间的金属氧化物衬底，其具有导电裸片夹或设置在金属氧化物衬底和金属氧化物衬底之间的一个或多个电互连迹线半导体芯片的第一表面。散热部件可以包括散热器或适配器板，散热器可以耦合到适配器板。导电芯片夹或电迹线为半导体管芯的第一表面提供电连接，同时金属氧化物衬底将电芯与散热部件绝缘，并提供高导热性的路径在模具和散热部件之间。半导体管芯的第二表面可以自由地连接到电路板，或者可以将引线框架或互连衬底附接到其上。

43. 发明申请

US20090072362A1 THERMAL ENHANCED UPPER AND DUAL HEAT SINK EXPOSED MOLDED LEADLESS PACKAGE 有权
标题翻译：热增强型和双重散热模具无铅包装
公开(公告)号：US20090072362A1
公开(公告)日：2009-03-19
申请号：US12170523
申请日：2008-07-10
申请人： Chung-Lin Wu , Rajeev D. Joshi
发明人： Chung-Lin Wu , Rajeev D. Joshi
IPC分类号： H01L23/34 , H01L21/50
CPC分类号： H01L21/561 , H01L21/4828 , H01L23/4334 , H01L23/49548 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2221/68377 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49113 , H01L2224/73265 , H01L2224/83 , H01L2224/85 , H01L2224/92247 , H01L2224/97 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.
摘要翻译：半导体封装包括半导体器件30和模制的上部散热器10.散热器具有面向半导体器件的内表面16和至少部分地暴露于封装器件周围环境的外表面15。环形平面基座11围绕凸出或突出的中心区域12.该区域由基座11的平面支承在四个倾斜壁13.1-13.4之上。壁相对于平面环形基座呈锐角倾斜，并朝向上散热片10的中心倾斜。环形基座11的外周围是四个支撑臂18.1-18.4。支撑臂相对于平面环形基座11的内表面16以钝角设置。

44. 发明授权

US07468548B2 Thermal enhanced upper and dual heat sink exposed molded leadless package 失效
标题翻译：热增强型上，下两个散热片裸露无铅封装
公开(公告)号：US07468548B2
公开(公告)日：2008-12-23
申请号：US11299270
申请日：2005-12-09
申请人： Chung-Lin Wu , Rajeev D. Joshi
发明人： Chung-Lin Wu , Rajeev D. Joshi
IPC分类号： H01L23/495
CPC分类号： H01L21/561 , H01L21/4828 , H01L23/4334 , H01L23/49548 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2221/68377 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49113 , H01L2224/73265 , H01L2224/83 , H01L2224/85 , H01L2224/92247 , H01L2224/97 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.
摘要翻译：半导体封装包括半导体器件30和模制的上部散热器10.散热器具有面向半导体器件的内表面16和至少部分地暴露于封装器件周围环境的外表面15。环形平面基座11围绕凸出或突出的中心区域12.该区域由基座11的平面支承在四个倾斜壁13.1-13.4之上。壁相对于平面环形基座呈锐角倾斜，并朝向上散热片10的中心倾斜。环形基座11的外周围是四个支撑臂18.1-18.4。支撑臂相对于平面环形基座11的内表面16以钝角设置。

45. 发明申请

US20080054461A1 RELIABLE WAFER-LEVEL CHIP-SCALE PACKAGE SOLDER BUMP STRUCTURE IN A PACKAGED SEMICONDUCTOR DEVICE 审中-公开
标题翻译：包装半导体器件中可靠的水平切片尺寸包装焊接结构
公开(公告)号：US20080054461A1
公开(公告)日：2008-03-06
申请号：US11847512
申请日：2007-08-30
申请人： Dennis Lang , Sonbol Vaziri , James Naylor , Eric Woolsey , Chung-Lin Wu , Mike Gruenhagen , Neill Thornton
发明人： Dennis Lang , Sonbol Vaziri , James Naylor , Eric Woolsey , Chung-Lin Wu , Mike Gruenhagen , Neill Thornton
IPC分类号： H01L23/48 , H01L21/00
CPC分类号： H01L24/05 , H01L23/3114 , H01L23/3192 , H01L24/11 , H01L24/12 , H01L2224/0401 , H01L2224/05022 , H01L2224/05567 , H01L2224/05571 , H01L2224/05572 , H01L2224/05599 , H01L2224/13006 , H01L2224/13022 , H01L2224/13023 , H01L2224/131 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2224/13099 , H01L2924/00012 , H01L2224/05552
摘要： A wafer level chip scale package (WLCSP) includes a packaged semiconductor device with a plurality of solder bump pads, patterned passivation regions above each of the solder bump pads, a patterned under bump metallization (UBM) region on each of the solder bump pads and the passivation regions, a polyimide region over a portion of the UBM regions and the passivation regions, solder bumps formed on each of the UBM regions, and encapsulation material surrounding the semiconductor die except for at least a portion of each of the solder bumps.
摘要翻译：晶片级芯片级封装（WLCSP）包括具有多个焊料凸块焊盘的封装半导体器件，每个焊料凸块焊盘上方的图案化钝化区域，每个焊料凸块焊盘上的图案化凸块下金属化（UBM）区域，以及钝化区域，UBM区域和钝化区域的一部分上的聚酰亚胺区域，形成在每个UBM区域上的焊料凸块以及围绕半导体管芯的封装材料，除了每个焊料凸块的至少一部分之外。

46. 发明申请

US20070072347A1 METHOD OF ASSEMBLY FOR MULTI-FLIP CHIP ON LEAD FRAME ON OVERMOLDED IC PACKAGE 失效
标题翻译：针对过度封装的IC封装上的引线框架上的多片芯片组装方法
公开(公告)号：US20070072347A1
公开(公告)日：2007-03-29
申请号：US11560935
申请日：2006-11-17
申请人： Jonathan Noquil , Seung Choi , Rajeev Joshi , Chung-Lin Wu
发明人： Jonathan Noquil , Seung Choi , Rajeev Joshi , Chung-Lin Wu
IPC分类号： H01L21/00
CPC分类号： H01L25/16 , H01L23/3128 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/16 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： A multichip module package uses bond wire with plastic resin on one side of a lead frame to package an integrated circuit and flip chip techniques to attach one or more mosfets to the other side of the lead frame. The assembled multichip module 30 has an integrated circuit controller 14 on a central die pad. Wire bonds 16 extend from contact areas on the integrated circuit to outer leads 2.6 of the lead frame 10. On the opposite, lower side of the central die pad, the sources and gates of the mosfets 24, 26 are bump or stud attached to the half etched regions of the lead frame. The drains 36 of the mosfets and the ball contacts 22.1 on the outer leads are soldered to a printed circuit board.
摘要翻译：多芯片模块封装在引线框架的一侧使用与塑料树脂的接合线来封装集成电路和倒装芯片技术，以将一个或多个mosfet连接到引线框架的另一侧。组装的多芯片模块30在中央芯片焊盘上具有集成电路控制器14。线接合16从集成电路的接触区域延伸到引线框架10的外引线2.6。在相对的中央管芯焊盘的下侧，MOSFET45,26的源极和栅极是连接到引线框架的半蚀刻区域的凸起或螺柱。 mosfets的漏极36和外引线上的球接触件22.1被焊接到印刷电路板。

47. 发明申请

US20050127483A1 Thin, thermally enhanced flip chip in a leaded molded package 有权
公开(公告)号：US20050127483A1
公开(公告)日：2005-06-16
申请号：US11048314
申请日：2005-01-31
申请人： Rajeev Joshi , Chung-Lin Wu
发明人： Rajeev Joshi , Chung-Lin Wu
IPC分类号： H01L23/29 , H01L23/31 , H01L23/48 , H01L23/495 , H01L23/50 , H01L21/48
CPC分类号： H01L23/495 , H01L23/49548 , H01L23/49555 , H01L23/49562 , H01L23/49568 , H01L24/34 , H01L24/37 , H01L2224/16 , H01L2224/16245 , H01L2224/37599 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/37099
摘要： Embodiments of the invention are directed to semiconductor die packages. One embodiment of the invention is directed to a semiconductor die package including, (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die, where the molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.

48. 发明授权

US06867481B2 Lead frame structure with aperture or groove for flip chip in a leaded molded package 失效
标题翻译：引线框架结构，带引线模制封装中的倒装芯片的孔或凹槽
公开(公告)号：US06867481B2
公开(公告)日：2005-03-15
申请号：US10411688
申请日：2003-04-11
申请人： Rajeev Joshi , Chung-Lin Wu
发明人： Rajeev Joshi , Chung-Lin Wu
IPC分类号： H01L21/60 , H01L23/495 , H01L23/28
CPC分类号： H01L24/40 , H01L21/565 , H01L23/49503 , H01L23/49548 , H01L23/49562 , H01L24/37 , H01L24/81 , H01L2224/16 , H01L2224/16245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/81801 , H01L2224/83801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/19043 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/37099
摘要： A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.
摘要翻译：公开了一种半导体管芯封装。在一个实施例中，管芯封装包括包括第一表面和第二表面的半导体管芯，以及具有管芯附着区域的引线框架结构以及远离管芯附着区域延伸的多个引线。管芯附着区域包括一个或多个孔。成型材料围绕引线框架结构的芯片附接区域和半导体管芯的至少一部分。成型材料也在一个或多个孔内。

49. 发明授权

US5645668A Method of forming composite articles using a mandrel assembly 失效
标题翻译：使用心轴组件形成复合制品的方法
公开(公告)号：US5645668A
公开(公告)日：1997-07-08
申请号：US510454
申请日：1995-08-02
申请人： Chin-I Lin , Chung-Lin Wu , Rong-Shian Liu , Gou-Don Chu
发明人： Chin-I Lin , Chung-Lin Wu , Rong-Shian Liu , Gou-Don Chu
IPC分类号： B29C70/16 , B29C33/48 , B29C53/82 , B29C70/06 , B29C70/32 , B29K105/08 , B29L22/00 , B65H81/00
CPC分类号： B29C70/32 , B29C53/821 , B29C53/824 , B29C33/48
摘要： A mandrel assembly has a hollow main tube and two annular sleeves, wherein an inner diameter of the two annular sleeves is larger than an outer diameter of the two main tube ends. The two annular sleeves are sleeved respectively on the two main tube ends, which can be easily disengaged from the mandrel assembly when applied with an external force.
摘要翻译：心轴组件具有中空主管和两个环形套筒，其中两个环形套筒的内径大于两个主管端部的外径。两个环形套筒分别套在两个主管端上，当外力施加时，它们可以容易地从心轴组件脱离。

50. 发明授权

US09378130B2 Data writing method, and memory controller and memory storage apparatus using the same 有权
标题翻译：数据写入方法，以及使用其的存储器控制器和存储器存储装置
公开(公告)号：US09378130B2
公开(公告)日：2016-06-28
申请号：US13366271
申请日：2012-02-04
申请人： Chung-Lin Wu , Yi-Hsiang Huang
发明人： Chung-Lin Wu , Yi-Hsiang Huang
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7203 , G06F2212/7205
摘要： A data writing method for a rewritable non-volatile memory module, and a memory controller and a memory storage apparatus using the same are provided. The method includes partitioning physical blocks of the rewritable non-volatile memory module into a data area and a spare area and configuring logical blocks. The method also includes selecting physical blocks from the spare area as spare physical blocks corresponding to a logical block and using only lower physical pages of the spare physical blocks to store updated data that is to be written into the logical block. The method further includes moving valid data of all logical pages of the logical block into a physical block of the data area, wherein each lower physical page and an upper physical page corresponding thereto in the physical block are programmed together. Accordingly, the method can effectively improve the speed and reliability of writing data.
摘要翻译：提供了一种用于可重写非易失性存储器模块的数据写入方法，以及存储器控制器和使用其的存储器存储装置。该方法包括将可重写非易失性存储器模块的物理块划分为数据区和备用区并配置逻辑块。该方法还包括从备用区选择物理块作为对应于逻辑块的备用物理块，并且仅使用备用物理块的较低物理页来存储要写入逻辑块的更新数据。该方法还包括将逻辑块的所有逻辑页的有效数据移动到数据区的物理块中，其中在物理块中与之对应的每个下部物理页和上部物理页一起编程。因此，该方法可以有效地提高写入数据的速度和可靠性。

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