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41. 发明授权

US08609529B2 Fabrication method and structure of through silicon via 有权
标题翻译：通过硅通孔的制造方法和结构
公开(公告)号：US08609529B2
公开(公告)日：2013-12-17
申请号：US13363390
申请日：2012-02-01
申请人： Chin-Fu Lin , Chun-Yuan Wu , Chih-Chien Liu , Teng-Chun Tsai , Chin-Cheng Chien
发明人： Chin-Fu Lin , Chun-Yuan Wu , Chih-Chien Liu , Teng-Chun Tsai , Chin-Cheng Chien
IPC分类号： H01L21/4763
CPC分类号： H01L21/3085 , H01L21/3086 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a through silicon via (TSV) structure, in which, a patterned mask is formed on a substrate, the patterned mask has an opening, a spacer-shaped structure is formed on a sidewall of the opening, and a via hole having a relatively enlarged opening is formed by etching the spacer-shaped structure and the substrate through the opening after the spacer-shaped structure is formed. A TSV structure, in which, a via hole has an opening portion and a body portion, the opening portion is a relatively enlarged opening and has a tapered shape having an opening size of an upper portion greater than an opening size of a lower portion.
摘要翻译：一种制造贯穿硅通孔（TSV）结构的方法，其中在基板上形成图案化掩模，所述图案化掩模具有开口，在所述开口的侧壁上形成间隔物结构，并且所述通孔通过在形成间隔物结构之后通过开口蚀刻间隔物结构和基底而形成具有相对扩大的开口。 TSV结构，其中通孔具有开口部分和主体部分，所述开口部分是相对扩大的开口，并且具有开口尺寸大于下部开口尺寸的上部开口尺寸的锥形形状。

42. 发明申请

US20130207122A1 METHOD FOR FABRICATING FINFETS AND SEMICONDUCTOR STRUCTURE FABRICATED USING THE METHOD 有权
标题翻译：使用该方法制造FinFET和半导体结构的方法
公开(公告)号：US20130207122A1
公开(公告)日：2013-08-15
申请号：US13370231
申请日：2012-02-09
申请人： Chin-Fu Lin , Chin-Cheng Chien , Chun-Yuan Wu , Teng-Chun Tsai , Chih-Chien Liu
发明人： Chin-Fu Lin , Chin-Cheng Chien , Chun-Yuan Wu , Teng-Chun Tsai , Chih-Chien Liu
IPC分类号： H01L21/764 , H01L29/24
CPC分类号： H01L29/785 , H01L21/02381 , H01L21/02532 , H01L21/02636 , H01L21/31111 , H01L21/31116 , H01L21/3115 , H01L21/3141 , H01L21/3185 , H01L21/764 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L27/10879 , H01L29/1095 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66795
摘要： A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method.
摘要翻译：描述了制造FinFET的方法。图案化半导体衬底以形成奇数鳍片。间隔件形成在基底上和奇数翅片的侧壁上，其中每个间隔件具有基本垂直的侧壁。然后在间隔件之间的基板上均匀形成翅片。还描述了用于形成FinFET的半导体结构，其使用上述方法制造。

43. 发明授权

US08441072B2 Non-planar semiconductor structure and fabrication method thereof 有权
标题翻译：非平面半导体结构及其制造方法
公开(公告)号：US08441072B2
公开(公告)日：2013-05-14
申请号：US13224344
申请日：2011-09-02
申请人： Shih-Hung Tsai , Chien-Ting Lin , Chin-Cheng Chien , Chin-Fu Lin , Chih-Chien Liu , Teng-Chun Tsai , Chun-Yuan Wu
发明人： Shih-Hung Tsai , Chien-Ting Lin , Chin-Cheng Chien , Chin-Fu Lin , Chih-Chien Liu , Teng-Chun Tsai , Chun-Yuan Wu
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L29/66795
摘要： A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.
摘要翻译：非平面半导体结构包括衬底，至少两个鳍状结构，至少一个隔离结构和多个外延层。鳍状结构位于基底上。隔离结构位于鳍状结构之间，隔离结构具有含氮层。外延层分别覆盖了鳍状结构的一部分并且位于含氮层上。还提供了用于形成半导体结构的非平面半导体工艺。

44. 发明申请

US20130020648A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130020648A1
公开(公告)日：2013-01-24
申请号：US13185517
申请日：2011-07-19
申请人： Chun-Yuan Wu , Chih-Chien Liu
发明人： Chun-Yuan Wu , Chih-Chien Liu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823412 , H01L21/76224 , H01L21/76801 , H01L21/823418 , H01L21/823475 , H01L21/823481 , H01L27/088 , H01L29/7843 , H01L29/7846
摘要： A semiconductor device is disclosed. The semiconductor device includes: a substrate; a metal-oxide semiconductor (MOS) transistor disposed in the substrate; and a shallow trench isolation (STI) disposed in the substrate and around the MOS transistor, in which the STI comprises a stress material.
摘要翻译：公开了一种半导体器件。半导体器件包括：衬底; 设置在所述基板中的金属氧化物半导体（MOS）晶体管; 以及设置在衬底中并围绕MOS晶体管的浅沟槽隔离（STI），其中STI包括应力材料。

45. 发明申请

US20120319198A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120319198A1
公开(公告)日：2012-12-20
申请号：US13161503
申请日：2011-06-16
申请人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
发明人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L21/28158 , H01L21/28114 , H01L21/28185 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/49 , H01L29/4966 , H01L29/4983 , H01L29/51 , H01L29/517 , H01L29/66545
摘要： A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.
摘要翻译：提供了包括基板，间隔物和具有U形轮廓的高k电介质层的半导体器件。位于基板上的间隔件围绕并限定沟槽。具有U形轮廓的高k电介质层位于沟槽中，并且具有U形轮廓的高k电介质层露出沟槽的侧壁的上部。

46. 发明申请

US20120264306A1 Method of Forming Opening on Semiconductor Substrate 有权
标题翻译：在半导体基板上形成开口的方法
公开(公告)号：US20120264306A1
公开(公告)日：2012-10-18
申请号：US13087379
申请日：2011-04-15
申请人： Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Po-Chun Chen
发明人： Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Po-Chun Chen
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/76802
摘要： The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.
摘要翻译：本发明提供一种在半导体衬底上形成开口的方法。首先，提供基板。然后在基板上形成介电层和盖层。电介质层的厚度和盖层的厚度之比基本上在15和1.5之间。接下来，在盖层上形成图案化的氮化硼层。最后，通过使用图案化的硬掩模作为掩模来执行蚀刻工艺，以蚀刻覆盖层和电介质层，以在盖层和电介质层中形成开口。

47. 发明申请

US20120248507A1 METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：金属门结构及其制造方法
公开(公告)号：US20120248507A1
公开(公告)日：2012-10-04
申请号：US13072795
申请日：2011-03-28
申请人： Chih-Chien Liu , Chun-Yuan Wu , Chin-Fu Lin , Teng-Chun Tsai , Chin-Cheng Chien
发明人： Chih-Chien Liu , Chun-Yuan Wu , Chin-Fu Lin , Teng-Chun Tsai , Chin-Cheng Chien
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/517 , H01L21/28185 , H01L29/513 , H01L29/66545
摘要： A manufacturing method of a metal gate structure includes providing a substrate having at least a first metal oxide layer formed thereon, and transferring the surface of the first metal oxide layer into a second metal oxide layer. The first metal oxide layer includes a metal oxide (M1Ox) of a first metal (M1) and the second metal oxide layer includes a metal oxide ((M1M2Oy) of the first metal and a second metal (M2).
摘要翻译：金属栅极结构的制造方法包括提供具有形成在其上的至少第一金属氧化物层的基板，并将第一金属氧化物层的表面转移到第二金属氧化物层中。第一金属氧化物层包括第一金属（M1）的金属氧化物（M1Ox），第二金属氧化物层包括第一金属的金属氧化物（（M1M2Oy））和第二金属（M2）。

48. 发明申请

US20090225490A1 CAPACITOR STRUCTURE 审中-公开
标题翻译：电容结构
公开(公告)号：US20090225490A1
公开(公告)日：2009-09-10
申请号：US12043135
申请日：2008-03-06
申请人： Tsuoe-Hsiang Liao , Huo-Tieh Lu , Yu-Fang Chien , Chih-Chien Liu , Pei-Lin Kuo , Yu-Ru Yang
发明人： Tsuoe-Hsiang Liao , Huo-Tieh Lu , Yu-Fang Chien , Chih-Chien Liu , Pei-Lin Kuo , Yu-Ru Yang
IPC分类号： H01G4/005 , H01G4/00
CPC分类号： H01G4/232 , H01G4/012 , H01G4/30 , H01G4/33 , H01L23/5222 , H01L27/0207 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure has a first electrode and a second electrode, which does not electrically connect to the first electrode. The first electrode has a plurality of first meshed conductive structures. The first meshed conductive structures have the same layout pattern, and are electrically connected to each other. The second electrode has a plurality of second meshed conductive structures. The second meshed conductive structures have the same layout pattern, and are electrically connected to each other. The first meshed conductive structures and the second meshed conductive structures are alternately stacked.
摘要翻译：电容器结构具有不与第一电极电连接的第一电极和第二电极。第一电极具有多个第一网状导电结构。第一网状导电结构具有相同的布局图案，并且彼此电连接。第二电极具有多个第二网状导电结构。第二网状导电结构具有相同的布局图案，并且彼此电连接。第一网状导电结构和第二网状导电结构交替堆叠。

49. 发明申请

US20080246061A1 STRESS LAYER STRUCTURE 审中-公开
标题翻译：应力层结构
公开(公告)号：US20080246061A1
公开(公告)日：2008-10-09
申请号：US11695761
申请日：2007-04-03
申请人： Chin-Sheng Yang , Chih-Chien Liu
发明人： Chin-Sheng Yang , Chih-Chien Liu
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L27/0207 , H01L29/7843
摘要： A stress layer structure disposed on a substrate including a device region and a non-device region is provided. The device region includes active regions and a non-active region. The stress layer structure has stress patterns, at least one partition line, and at least one dummy stress pattern. Each of the stress patterns is disposed on the substrate of each of the active regions, respectively. The partition line exposes a portion of the substrate and divides the two adjacent stress patterns. The dummy stress pattern is disposed on the substrate in the partition line.
摘要翻译：提供了设置在包括器件区域和非器件区域的衬底上的应力层结构。器件区域包括有源区和非有源区。应力层结构具有应力模式，至少一个分隔线和至少一个虚拟应力模式。每个应力图案分别设置在每个有源区的基板上。分隔线暴露基板的一部分并且划分两个相邻的应力图案。虚拟应力图案设置在分割线中的基板上。

50. 发明授权

US07418609B2 Method for instant on multimedia playing 有权
标题翻译：多媒体播放方法
公开(公告)号：US07418609B2
公开(公告)日：2008-08-26
申请号：US11307393
申请日：2006-02-06
申请人： Yi-Chang Chen , Chih-Chien Liu
发明人： Yi-Chang Chen , Chih-Chien Liu
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , H04N21/4143 , H04N21/42646 , H04N21/4325 , H04N21/4432 , H04N21/4435 , H04N21/482 , H04N21/8193
摘要： A method for instant on multimedia playing is provided, which enables a computer to selectively enter an operation mode of an IOMP (Instant On Multimedia Player) program when it enters a power conservation mode. First, a computer system stays in the power conservation mode, until an IOMP activating signal has been received. Next, the computer system saves the hardware information of the computer into a memory. And then a processor of the computer reads an IOMP program from another memory and executes the IOMP program to produce and display a human-computer interface menu, which is provided for users to select files for playing. Next, the processor executes the IOMP program to play the files selected previously. Finally, upon the receipt of a recovery instruction, the computer system saves the hardware information back into the computer to recover the computer to the power conservation mode.
摘要翻译：提供一种用于即时多媒体播放的方法，其使得计算机能够在进入功率节省模式时选择性地进入IOMP（即时多媒体播放器）程序的操作模式。首先，计算机系统保持在省电模式，直到接收到IOMP激活信号。接下来，计算机系统将计算机的硬件信息保存到存储器中。然后，计算机的处理器从另一个存储器读取IOMP程序，并执行IOMP程序以产生并显示人机界面菜单，该菜单为用户选择要播放的文件。接下来，处理器执行IOMP程序来播放以前选择的文件。最后，在接收到恢复指令后，计算机系统将硬件信息保存回计算机，以将计算机恢复到省电模式。

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