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41. 发明授权

US09039278B2 Ratio meter of a thermal sensor 有权
标题翻译：热传感器的比率计
公开(公告)号：US09039278B2
公开(公告)日：2015-05-26
申请号：US13754151
申请日：2013-01-30
申请人： Mei-Chen Chuang , Jui-Cheng Huang , Alan Roth
发明人： Mei-Chen Chuang , Jui-Cheng Huang , Alan Roth
IPC分类号： G01K7/00 , G01L19/04 , G01R27/02 , G01K1/00
CPC分类号： G01K1/00 , G01K1/02 , G01K7/01 , G01K7/34 , G01K2219/00
摘要： A ratio meter includes a converter circuit, a first counter, a delay circuit, and a second counter. The converter circuit is configured to receive a temperature-independent signal, to convert the received temperature-independent signal into a first frequency signal during a first phase, to receive a temperature-dependent signal, and to convert the temperature-dependent signal into a second frequency signal during a second phase. The first counter is configured to receive the first frequency signal and to generate a control signal by counting a predetermined number of pulses of the first frequency signal count. The delay circuit is configured to delay the control signal for a predetermined time delay. The second counter is configured to receive the second frequency signal and to generate a count value by counting the second frequency signal.
摘要翻译：比率计包括转换器电路，第一计数器，延迟电路和第二计数器。转换器电路被配置为接收温度独立信号，以在第一阶段期间将接收到的与温度无关的信号转换为第一频率信号，以接收依赖于温度的信号，并将温度相关信号转换为第二频率信号频率信号在第二阶段。第一计数器被配置为接收第一频率信号并且通过对预定数量的第一频率信号计数的脉冲进行计数来产生控制信号。延迟电路被配置为延迟控制信号达预定的时间延迟。第二计数器被配置为接收第二频率信号并且通过对第二频率信号进行计数来产生计数值。

42. 发明授权

US08519684B2 Integrated circuits for converting a high voltage level to a low voltage level 有权
标题翻译：用于将高电压电平转换为低电压电平的集成电路
公开(公告)号：US08519684B2
公开(公告)日：2013-08-27
申请号：US12877535
申请日：2010-09-08
申请人： Mei-Chen Chuang , Alan Roth
发明人： Mei-Chen Chuang , Alan Roth
IPC分类号： G05F1/40
CPC分类号： H02M3/158 , G05F1/462 , H02M3/157 , H02M3/1588 , H05B33/0815 , Y02B70/1466
摘要： An integrated circuit includes a high side driver and a low side driver. The low side driver is electrically coupled with the high side driver. A circuit is electrically coupled with the high side driver and a first node between the high side driver and the low side driver. The circuit is configured to substantially turn off the high side driver if the high side driver leaves a cutoff region of the high side driver during a tri-state mode.
摘要翻译：集成电路包括高侧驱动器和低侧驱动器。低侧驱动器与高侧驱动器电耦合。电路与高侧驱动器和高侧驱动器和低侧驱动器之间的第一节点电耦合。如果高侧驱动器在三态模式期间离开高侧驱动器的截止区域，则该电路被配置为基本上关闭高侧驱动器。

43. 发明授权

US07643324B2 Method and apparatus for performing variable word width searches in a content addressable memory 有权
标题翻译：用于在内容可寻址存储器中执行可变字宽搜索的方法和装置
公开(公告)号：US07643324B2
公开(公告)日：2010-01-05
申请号：US11367507
申请日：2006-03-06
申请人： Alan Roth
发明人： Alan Roth
IPC分类号： G11C15/00 , G06F13/28
CPC分类号： G11C15/04 , G11C15/00
摘要： A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.
摘要翻译：一种用于使用可变宽度搜索数据执行搜索操作的内容可寻址存储器（CAM），所述CAM包括多个CAM单元阵列，每个阵列耦合到相应的子搜索数据总线，所述子搜索总线被限制为形成主搜索数据总线，应用搜索数据; 接收来自相应CAM阵列的匹配线信号的选择器电路，匹配线信号表示在相关联的CAM阵列中形成的搜索和比较的结果，选择器电路响应于选择一个或多个所述匹配的模式选择信号线路输出信号被切换到优先编码器和多重匹配解算器（PE-MMR），其中在第一模式中，匹配线输出信号被切换到所述PE-MMR，并且在第二模式中，来自所选择的匹配线输出信号组阵列被切换到所述PE-MMR。

44. 发明授权

US07350137B2 Method and circuit for error correction in CAM cells 失效
标题翻译： CAM单元纠错方法与电路
公开(公告)号：US07350137B2
公开(公告)日：2008-03-25
申请号：US11313661
申请日：2005-12-22
申请人： Richard Foss , Alan Roth
发明人： Richard Foss , Alan Roth
IPC分类号： G11C29/00
CPC分类号： G06F11/1064 , G11C15/00
摘要： A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array. The method includes the following steps: a row parity bit corresponding to a parity of a first plurality of bits stored along a row of CAM cells is stored; a column parity bit corresponding to the parity of a second plurality of bits stored along a column of CAM cells is stored; a parity of the first plurality of bits is read and generated and the generated parity is compared to the stored row parity bit, if the generated and stored parity bits do not match, columns of the array are cycled through; a parity of the second plurality of bits is read and generated and the generated parity is compared to the stored column parity bit until a mismatch is indicated; and, a bit located at an intersection of the mismatched row and column is inverted if the mismatch is indicated.
摘要翻译：提供了一种用于检测和校正内容可寻址存储器（CAM）单元阵列中的错误的方法和电路。阵列包括用于从阵列中读取，写入和搜索CAM单元的字线，搜索线，位线和匹配线。该方法包括以下步骤：存储对应于沿着一组CAM单元存储的第一多个比特的奇偶校验位的行奇偶校验位; 存储与沿着CAM单元的列存储的第二多个比特的奇偶校验相对应的列奇偶校验位; 读出并产生第一多个比特的奇偶校验，并且如果生成和存储的奇偶校验位不匹配，则将生成的奇偶校验与存储的行奇偶校验位进行比较，则阵列的列循环; 读取并生成第二多个比特的奇偶校验，并将生成的奇偶校验与存储的列奇偶校验位进行比较，直到指示不匹配为止; 并且如果指示不匹配，位于错配的行和列的交点处的位被反转。

45. 发明授权

US07188211B2 Block programmable priority encoder in a CAM 有权
标题翻译：在CAM中嵌入可编程优先编码器
公开(公告)号：US07188211B2
公开(公告)日：2007-03-06
申请号：US10724576
申请日：2003-12-01
申请人： Alan Roth , Sean Lord , Robert McKenzie , Dieter Haerle , Steven Smith
发明人： Alan Roth , Sean Lord , Robert McKenzie , Dieter Haerle , Steven Smith
IPC分类号： G06F12/00 , G06F9/00
CPC分类号： G11C15/00
摘要： A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.
摘要翻译：一种用于CAM的优先编码器（PE），包括多个PE块，每个PE块都接收与对应的数据阵列块中的数据条目相对应的多个匹配结果，并且用于基于物理上的数据来确定最高优先级数据条目的地址在CAM搜索与比较操作期间在数据阵列块中的位置存储用于分配给每个PE块的用户定义的优先级值的寄存器以及用于评估优先级值的装置和由多个PE块确定的地址以选择PE块具有最高优先级的数据输入。

46. 发明申请

US20050052907A1 Method and apparatus for performing variable word width searches in a content addressable memory 有权
标题翻译：用于在内容可寻址存储器中执行可变字宽搜索的方法和装置
公开(公告)号：US20050052907A1
公开(公告)日：2005-03-10
申请号：US10902687
申请日：2004-07-30
申请人： Alan Roth
发明人： Alan Roth
IPC分类号： G11C15/00 , G11C11/34
CPC分类号： G11C15/04 , G11C15/00
摘要： A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.
摘要翻译：一种用于使用可变宽度搜索数据执行搜索操作的内容可寻址存储器（CAM），所述CAM包括多个CAM单元阵列，每个阵列耦合到相应的子搜索数据总线，所述子搜索总线被限制为形成主搜索数据总线，应用搜索数据; 接收来自相应CAM阵列的匹配线信号的选择器电路，匹配线信号表示在相关联的CAM阵列中形成的搜索和比较的结果，选择器电路响应于选择一个或多个所述匹配的模式选择信号线路输出信号被切换到优先编码器和多重匹配解算器（PE-MMR），其中在第一模式中，匹配线输出信号被切换到所述PE-MMR，并且在第二模式中，来自所选择的匹配线输出信号组阵列被切换到所述PE-MMR。

47. 发明申请

US20050001744A1 Block programmable priority encoder in a CAM 有权
标题翻译：在CAM中嵌入可编程优先编码器
公开(公告)号：US20050001744A1
公开(公告)日：2005-01-06
申请号：US10724576
申请日：2003-12-01
申请人： Alan Roth , Sean Lord , Robert McKenzie , Dieter Haerle , Steve Smith
发明人： Alan Roth , Sean Lord , Robert McKenzie , Dieter Haerle , Steve Smith
IPC分类号： G11C15/00 , H03M7/00
CPC分类号： G11C15/00
摘要： A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.
摘要翻译：一种用于CAM的优先编码器（PE），包括多个PE块，每个PE块都接收与对应的数据阵列块中的数据条目相对应的多个匹配结果，并且用于基于物理上的数据来确定最高优先级数据条目的地址在CAM搜索与比较操作期间在数据阵列块中的位置存储用于分配给每个PE块的用户定义的优先级值的寄存器以及用于评估优先级值的装置和由多个PE块确定的地址以选择PE块具有最高优先级的数据输入。

48. 发明授权

US06771525B2 Method and apparatus for performing variable word width searches in a content addressable memory 有权
标题翻译：用于在内容可寻址存储器中执行可变字宽搜索的方法和装置
公开(公告)号：US06771525B2
公开(公告)日：2004-08-03
申请号：US10158196
申请日：2002-05-31
申请人： Alan Roth
发明人： Alan Roth
IPC分类号： G11C1500
CPC分类号： G11C15/04 , G11C15/00
摘要： A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.
摘要翻译：一种用于使用可变宽度搜索数据执行搜索操作的内容可寻址存储器（CAM），所述CAM包括多个CAM单元阵列，每个阵列耦合到相应的子搜索数据总线，所述子搜索总线被限制为形成主搜索数据总线，应用搜索数据; 接收来自相应CAM阵列的匹配线信号的选择器电路，匹配线信号表示在相关联的CAM阵列中形成的搜索和比较的结果，选择器电路响应于选择一个或多个所述匹配的模式选择信号线路输出信号被切换到优先编码器和多重匹配解算器（PE-MMR），其中在第一模式中，匹配线输出信号被切换到所述PE-MMR，并且在第二模式中，来自所选择的匹配线输出信号组阵列被切换到所述PE-MMR。

49. 发明授权

US06563727B1 Method and structure for reducing noise effects in content addressable memories 失效
标题翻译：用于减少内容可寻址存储器中的噪声影响的方法和结构
公开(公告)号：US06563727B1
公开(公告)日：2003-05-13
申请号：US10208011
申请日：2002-07-31
申请人： Alan Roth , Hamed Ghassemi
发明人： Alan Roth , Hamed Ghassemi
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： A method for reducing the coupling noise in a Content Addressable Memory (CAM), the CAM having a first bitline pair and a second bitline pair, both pairs aligned along a first axis; a first memory cell connected to the first bitline pair and a second memory cell to the second bitline pair; having a first match line and a first word line aligned along a second axis, the first match line and the first word line connecting the first and the second memory cells defining a first row in a first column; having a second row adjacent the first row, the second row comprising a third cell and a fourth cell, the third and fourth cells connecting the first and second bitline pairs and a second word line and a second match line, the method comprising arranging the first memory cell in a first orientation and the second memory cell in a second orientation, wherein the second orientation being a first axis mirror image to the first orientation; segmenting the first and second bitline pairs between the first row and the second row; adding a first twisting structure to the first bitline pair and a second twisting structure to the second bitline pair; arranging the third cell in a third orientation, the third orientation being rotated 180 degrees with respect to the first orientation; and arranging the fourth cell in a fourth orientation, the fourth orientation being rotated 180 degrees with respect to the second orientation.
摘要翻译：一种用于减少内容可寻址存储器（CAM）中的耦合噪声的方法，所述CAM具有沿着第一轴对准的第一位线对和第二位线对; 连接到第一位线对的第一存储器单元和到第二位线对的第二存储器单元; 具有沿着第二轴对准的第一匹配线和第一字线，所述第一匹配线和所述第一字线连接限定第一列中的第一行的所述第一和第二存储器单元; 具有与第一行相邻的第二行，第二行包括第三单元和第四单元，第三单元和第四单元连接第一和第二位线对以及第二字线和第二匹配线，该方法包括将第一行存储单元，并且所述第二存储单元处于第二取向，其中所述第二取向是到所述第一取向的第一轴镜像; 分割第一行和第二行之间的第一和第二位线对; 将第一扭转结构添加到所述第一位线对，将第二扭转结构添加到所述第二位线对; 以第三方向布置第三单元，第三取向相对于第一取向旋转180度; 以及将所述第四单元格设置在第四取向中，所述第四取向相对于所述第二取向旋转180度。

50. 再颁专利

USRE43552E1 Block programmable priority encoder in a cam 有权
标题翻译：在凸轮中嵌入可编程优先编码器
公开(公告)号：USRE43552E1
公开(公告)日：2012-07-24
申请号：US12709198
申请日：2010-02-19
申请人： Alan Roth , Sean Lord , Robert McKenzie , Dieter Haerle , Steven Smith
发明人： Alan Roth , Sean Lord , Robert McKenzie , Dieter Haerle , Steven Smith
IPC分类号： G06F12/00
CPC分类号： G11C15/00
摘要： A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.
摘要翻译：一种用于CAM的优先编码器（PE），包括多个PE块，每个PE块都接收与对应的数据阵列块中的数据条目相对应的多个匹配结果，并且用于基于物理上的数据来确定最高优先级数据条目的地址在CAM搜索与比较操作期间在数据阵列块中的位置存储用于分配给每个PE块的用户定义的优先级值的寄存器以及用于评估优先级值的装置和由多个PE块确定的地址以选择PE块具有最高优先级的数据输入。

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