专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US08111465B2 Electrofluidic devices, visual displays, and methods for making and operating such electrofluidic devices 有权
标题翻译：电流体装置，视觉显示器以及用于制造和操作这种电流流体装置的方法
公开(公告)号：US08111465B2
公开(公告)日：2012-02-07
申请号：US12677653
申请日：2008-09-12
申请人： Jason Heikenfeld , Bo Sun , April Milarcik , George Robertson , Russell Schwartz
发明人： Jason Heikenfeld , Bo Sun , April Milarcik , George Robertson , Russell Schwartz
IPC分类号： G02B1/06
CPC分类号： G02B26/005
摘要： Electrofluidic devices, visual displays formed from the electrofluidic devices, and methods for making and operating such electrofluidic devices Each electrofluidic device has a fluid vessel with first and second regions that contain an electrically conductive polar fluid and a non-polar fluid The polar and/or the non-polar fluids are externally visible external through a viewable area of the second region A voltage source is electrically connected to a capacitor having a hydrophobic surface that contacts the polar fluid and provides a first principal radius of curvature of the polar fluid that is convex and smaller than a second principal radius of curvature of the polar fluid in the first region The voltage source applies an electromechanical force to the polar fluid, thereby transferring the polar fluid from the first region to the second region and causing a spectral property of light transferred through the viewable area to change.
摘要翻译：电流体装置，由电流流体装置形成的视觉显示器，以及用于制造和操作这种电流流体装置的方法。每个电流流体装置具有流体容器，其具有包含导电极性流体和非极性流体的第一和第二区域。极性和/或非极性流体在外部通过第二区域的可视区域外部可见。电压源电连接到具有与极性流体接触的疏水表面的电容器，并且提供极性流体的凸起的第一主曲率半径并且小于第一区域中的极性流体的第二主曲率半径。电压源对极性流体施加机电力，从而将极性流体从第一区域传递到第二区域，并且使通过可视区域传输的光的光谱特性发生变化。

42. 发明申请

US20110301813A1 CUSTOMIZABLE VIRTUAL LANE MARK DISPLAY 审中-公开
标题翻译：可定制虚拟LANE MARK显示
公开(公告)号：US20110301813A1
公开(公告)日：2011-12-08
申请号：US12795131
申请日：2010-06-07
申请人： Bo Sun , Daniel P. Tran , Christopher A. Arms , Carolina M. Giannotti , Justin McBride , Nhi Van Pham , Martin E. Nespolo , Silviu Pala , Michael Chachich
发明人： Bo Sun , Daniel P. Tran , Christopher A. Arms , Carolina M. Giannotti , Justin McBride , Nhi Van Pham , Martin E. Nespolo , Silviu Pala , Michael Chachich
IPC分类号： G09G5/00 , B62D15/02 , H04N7/18 , G06F7/00
CPC分类号： B62D15/029 , G01C21/3658 , H04N7/18
摘要： A method of displaying virtual lane markings relative to a vehicle position within a roadway lane may entail reading vehicle data such as speed into a vehicle control module, determining if the vehicle data is above a particular threshold, switching a virtual lane display switch, determining weather conditions, and displaying virtual lane markings upon a vehicle windshield based upon a result of determining weather conditions. Detecting actual lane markings on one or both of a left side of the roadway lane and a right side of the roadway lane may be accomplished with a vehicle-mounted camera. Moreover, determining whether a steering wheel has rotated a predetermined number of degrees may further play a role in displaying the virtual lane markings on a windshield of the vehicle. From a driver viewing perspective through a windshield, virtual lane markings may be displayed on the windshield to overlay actual lane markings.
摘要翻译：相对于道路车道内的车辆位置显示虚拟车道标记的方法可能需要将诸如速度的车辆数据读取到车辆控制模块中，确定车辆数据是否高于特定阈值，切换虚拟车道显示开关，确定天气条件，并且基于确定天气条件的结果在车辆挡风玻璃上显示虚拟车道标记。在道路车道的左侧和道路车道的右侧的一侧或两侧检测实际车道标记可以使用车载摄像机来实现。此外，确定方向盘是否已经旋转了预定数量的角度还可以在车辆的挡风玻璃上显示虚拟车道标记方面发挥作用。从驾驶员视角透视挡风玻璃，可以在挡风玻璃上显示虚拟车道标记，以覆盖实际车道标记。

43. 发明授权

US08045669B2 Digital phase-locked loop operating based on fractional input and output phases 有权
$Digital phase-locked loop operating based on fractional input and output phases$
标题翻译：基于分数输入和输出阶段的数字锁相环操作
公开(公告)号：US08045669B2
公开(公告)日：2011-10-25
申请号：US11947587
申请日：2007-11-29
申请人： Gary John Ballantyne , Bo Sun
发明人： Gary John Ballantyne , Bo Sun
IPC分类号： H03D3/04
CPC分类号： H03L7/10 , H03L7/085 , H03L7/087 , H03L2207/50
摘要： In one aspect, a digital PLL (DPLL) operates based on fractional portions of input and output phases. The DPLL accumulates at least one input signal to obtain an input phase. The DPLL determines a fractional portion of an output phase based on a phase difference between an oscillator signal from an oscillator and a reference signal, e.g., using a time-to-digital converter (TDC). The DPLL determines a phase error based on the fractional portion of the input phase and the fractional portion of the output phase. The DPLL then generates a control signal for the oscillator based on the phase error. In another aspect, a DPLL includes a synthesized accumulator that determines a coarse output phase by keeping track of the number of oscillator signal cycles based on the reference signal.
摘要翻译：在一个方面，数字PLL（DPLL）基于输入和输出相位的小数部分进行操作。 DPLL累加至少一个输入信号以获得输入相位。 DPLL基于来自振荡器的振荡器信号与参考信号之间的相位差（例如使用时间 - 数字转换器（TDC））来确定输出相位的小数部分。 DPLL根据输入相位的小数部分和输出相位的小数部分确定相位误差。 DPLL然后基于相位误差产生振荡器的控制信号。在另一方面，DPLL包括合成的累加器，其通过基于参考信号跟踪振荡器信号周期的数量来确定粗略的输出相位。

44. 发明授权

US07978111B2 High resolution time-to-digital converter 有权
标题翻译：高分辨率时间 - 数字转换器
公开(公告)号：US07978111B2
公开(公告)日：2011-07-12
申请号：US12041426
申请日：2008-03-03
申请人： Bo Sun , Zixiang Yang
发明人： Bo Sun , Zixiang Yang
IPC分类号： H03K5/00 , H03M1/12
CPC分类号： G04F10/005
摘要： A time-to-digital converter (TDC) can have a resolution that is finer than the propagation delay of an inverter. In one example, a fractional-delay element circuit receives a TDC input signal and generates therefrom a second signal that is a time-shifted facsimile of a first signal. The first signal is supplied to a first delay line timestamp circuit (DLTC) and the second signal is supplied to a second DLTC. The first DLTC generates a first timestamp indicative of a time between an edge of a reference input signal to the TDC and an edge of the first signal. The second DLTC generates a second timestamp indicative of a time between the edge of the reference input signal and an edge of the second signal. The first and second timestamps are combined and together constitute a high-resolution overall TDC timestamp that has a finer resolution than either the first or second timestamps.
摘要翻译：时间 - 数字转换器（TDC）可以具有比逆变器的传播延迟更精细的分辨率。在一个示例中，分数延迟元件电路接收TDC输入信号并由此产生作为第一信号的时移传真的第二信号。第一信号被提供给第一延迟线时间戳电路（DLTC），第二信号被提供给第二DLTC。第一DLTC产生指示参考输入信号与TDC的边缘和第一信号的边缘之间的时间的第一时间戳。第二DLTC产生指示参考输入信号的边缘与第二信号的边缘之间的时间的第二时间戳。组合第一和第二时间戳并且一起构成具有比第一或第二时间戳更精细的分辨率的高分辨率整体TDC时间戳。

45. 发明授权

US07965111B2 Method and apparatus for divider unit synchronization 有权
标题翻译：分频器单元同步的方法和装置
公开(公告)号：US07965111B2
公开(公告)日：2011-06-21
申请号：US12111561
申请日：2008-04-29
申请人： Bo Sun , Sankaran Aniruddhan , Sriramgopal Sridhara
发明人： Bo Sun , Sankaran Aniruddhan , Sriramgopal Sridhara
IPC分类号： H03L7/00
CPC分类号： G06F1/12 , G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A method an apparatus for synchronizing phases of one or more divider units comprise powering on a master divider unit to provide a reference signal. A phase of a slave divider unit is synchronized to the reference signal from the master divider unit by providing a power on pulse at the slave divider unit, synchronizing the phase of the slave divider unit to the reference signal using a digitally controlled oscillator, and powering on the slave divider unit after a first predetermined delay period following a rising edge of the power on pulse. By synchronizing a slave divider unit to the reference signal from the master divider unit, any number of slave divider units may be powered on and in-phase with each other.
摘要翻译：一种用于同步一个或多个除法器单元的相位的装置的方法包括在主分频器单元上供电以提供参考信号。从分频器单元的相位通过在从分频器单元处提供通电脉冲而与来自主分频器单元的参考信号同步，使用数字控制的振荡器将从分频器单元的相位与参考信号同步，在通电脉冲的上升沿之后的第一预定延迟时段之后的从分频器单元上。通过将从属分频器单元与来自主分频器单元的参考信号同步，任何数量的从分频器单元可以通电并且彼此同相。

46. 发明申请

US20110143689A1 SIGNAL DECIMATION TECHNIQUES 有权
标题翻译：信号分解技术
公开(公告)号：US20110143689A1
公开(公告)日：2011-06-16
申请号：US12638822
申请日：2009-12-15
申请人： Gary J. Ballantyne , Jifeng Geng , Bo Sun
发明人： Gary J. Ballantyne , Jifeng Geng , Bo Sun
IPC分类号： H04B1/40 , H03B19/00
CPC分类号： H03B19/00 , H03D7/165 , H03L7/16
摘要： Techniques for decimating a first periodic signal to generate a second periodic signal. In an exemplary embodiment, the first periodic signal is divided by a configurable integer ratio divider, and the output of the divider is delayed by a configurable fractional delay. The configurable fractional delay may be noise-shaped using, e.g., sigma-delta modulation techniques to spread the quantization noise of the fractional delay over a wide bandwidth. In an exemplary embodiment, the first and second periodic signals may be used to generate the transmit (TX) and receive (RX) local oscillator (LO) signals for a communications transceiver from a single phase-locked loop (PLL) output.
摘要翻译：抽取第一周期信号以产生第二周期信号的技术。在示例性实施例中，第一周期信号由可配置的整数比除法器除以且分频器的输出被延迟可配置的分数延迟。使用例如Σ-Δ调制技术，可配置分数延迟可以是噪声形状，以在宽带宽上扩展分数延迟的量化噪声。在示例性实施例中，第一和第二周期信号可以用于从单个锁相环（PLL）输出生成通信收发器的发射（TX）和接收（RX）本地振荡器（LO）信号。

47. 发明申请

US20100208328A1 Electrofluidic Devices, Visual Displays, And Methods For Making And Operating Such Elecrofluidic Devices 有权
标题翻译：电流体装置，视觉显示器和用于制造和操作这种分流流体装置的方法
公开(公告)号：US20100208328A1
公开(公告)日：2010-08-19
申请号：US12677653
申请日：2008-09-12
申请人： Jason Heikenfeld , Bo Sun , April Milarcik , George Robertson , Russell Schwartz
发明人： Jason Heikenfeld , Bo Sun , April Milarcik , George Robertson , Russell Schwartz
IPC分类号： G02F1/23 , G02F1/01
CPC分类号： G02B26/005
摘要： Electrofluidic devices, visual displays formed from the electrofluidic devices, and methods for making and operating such electrofluidic devices Each electrofluidic device has a fluid vessel with first and second regions that contain an electrically conductive polar fluid and a non-polar fluid The polar and/or the non-polar fluids are externally visible external through a viewable area of the second region A voltage source is electrically connected to a capacitor having a hydrophobic surface that contacts the polar fluid and provides a first principal radius of curvature of the polar fluid that is convex and smaller than a second principal radius of curvature of the polar fluid in the first region The voltage source applies an electromechanical force to the polar fluid, thereby transferring the polar fluid from the first region to the second region and causing a spectral property of light transferred through the viewable area to change
摘要翻译：电流体装置，由电流流体装置形成的视觉显示器，以及用于制造和操作这种电流流体装置的方法。每个电流流体装置具有流体容器，其具有包含导电极性流体和非极性流体的第一和第二区域。极性和/或非极性流体在外部通过第二区域的可视区域外部可见。电压源电连接到具有与极性流体接触的疏水表面的电容器，并且提供极性流体的凸起的第一主曲率半径并且小于第一区域中的极性流体的第二主曲率半径。电压源对极性流体施加机电力，从而将极性流体从第一区域传递到第二区域，并且使通过可视区域传输的光的光谱特性发生变化。

48. 发明申请

US20090175399A1 DIGITAL PHASE-LOCKED LOOP WITH GATED TIME-TO-DIGITAL CONVERTER 有权
标题翻译：数字锁相环与定位的时间到数字转换器
公开(公告)号：US20090175399A1
公开(公告)日：2009-07-09
申请号：US11969359
申请日：2008-01-04
申请人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
发明人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
IPC分类号： H03D3/24
CPC分类号： H03L7/0802 , H03L7/087
摘要： A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.
摘要翻译：数字PLL（DPLL）包括时间 - 数字转换器（TDC）和控制单元。定期启用TDC以持续短时间量化相位信息，并在剩余时间内禁用TDC以降低功耗。 TDC接收第一时钟信号和第一参考信号，并提供指示第一时钟信号和第一参考信号之间的相位差的TDC输出。控制单元基于主参考信号生成使能信号，并使能和禁止具有使能信号的TDC。在一种设计中，控制单元延迟主参考信号以获得第一参考信号和第二参考信号，基于主参考信号和第二参考信号产生使能信号，并且将主时钟信号与使能信号以获得TDC的第一个时钟信号。

49. 发明申请

US20090161588A1 SYSTEMS AND METHODS FOR CONTROLLING THE VOLTAGE OF SIGNALS USED TO CONTROL POWER AMPLIFIERS 有权
标题翻译：用于控制用于控制功率放大器的信号电压的系统和方法
公开(公告)号：US20090161588A1
公开(公告)日：2009-06-25
申请号：US12133758
申请日：2008-06-05
申请人： David Maldonado , Puay Hoe See , Bo Sun , Guang Zhang , Brett C. Walker
发明人： David Maldonado , Puay Hoe See , Bo Sun , Guang Zhang , Brett C. Walker
IPC分类号： G08C17/02 , H04B7/216
CPC分类号： H04B1/0483 , H04B1/40 , H04B2001/0416
摘要： A method for controlling the voltage of signals used to control power amplifiers is described. A first multiplexer and a second multiplexer are set to an enabling signal. The first multiplexer is on a first integrated circuit and the second multiplexer is on a second integrated circuit. A command is written to the first multiplexer to set the first multiplexer to one of a plurality of control signals used to control a power amplifier. A command is written to the second multiplexer to select one of the plurality of control signals that maps to the first multiplexer. The second integrated circuit is connected to a power supply.
摘要翻译：描述了用于控制用于控制功率放大器的信号的电压的方法。第一多路复用器和第二多路复用器被设置为使能信号。第一多路复用器在第一集成电路上，第二多路复用器在第二集成电路上。一个命令被写入到第一多路复用器中，以将第一多路复用器设置成用于控制功率放大器的多个控制信号之一。一个命令被写入第二多路复用器以选择映射到第一多路复用器的多个控制信号之一。第二集成电路连接到电源。

50. 发明申请

US20090111409A1 DYNAMIC BIASING OF A VCO IN A PHASE-LOCKED LOOP 有权
标题翻译：在相位锁定环路中的VCO的动态偏移
公开(公告)号：US20090111409A1
公开(公告)日：2009-04-30
申请号：US11924318
申请日：2007-10-25
申请人： Bo Sun , Gurkanwal Singh Sahota , Yue Wu
发明人： Bo Sun , Gurkanwal Singh Sahota , Yue Wu
IPC分类号： H04B1/18
CPC分类号： H03L7/197 , H03J7/065 , H03L1/00 , H03L7/0802 , H03L7/0898 , H03L7/093 , H03L7/107 , H03L2207/06
摘要： A local oscillator includes a phase-locked loop. The phase-locked loop includes voltage controlled oscillator (VCO) and a novel VCO control circuit. The VCO control circuit may be programmable and configurable. In one example, an instruction is received onto the VCO control circuit to change the power state of the VCO. The instruction is issued by other circuitry in response to a detected change in RF channel conditions (for example, a change in a signal-to-noise determination) in a cellular telephone. In response, the VCO control circuit outputs control signals that gradually widen the loop bandwidth of the PLL, then gradually change the VCO bias current to change the VCO power state, and then narrow the loop bandwidth of the PLL back to its original bandwidth. The entire process of widening the PLL bandwidth, changing the VCO power state, and narrowing the PLL bandwidth occurs while the PLL remains locked.
摘要翻译：本地振荡器包括锁相环。锁相环包括压控振荡器（VCO）和新型VCO控制电路。 VCO控制电路可以是可编程的和可配置的。在一个示例中，在VCO控制电路上接收指令以改变VCO的功率状态。响应于在蜂窝电话中的RF信道条件（例如，信噪比确定的变化）的检测到的改变，由其他电路发出指令。作为响应，VCO控制电路输出逐渐拓宽PLL环路带宽的控制信号，然后逐渐改变VCO偏置电流，改变VCO功率状态，然后将PLL的环路带宽缩小回原来的带宽。当PLL保持锁定时，会发生整个PLL带宽扩大，改变VCO功率状态和缩小PLL带宽的过程。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式