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41. 发明申请

US20060258071A1 Methods of forming field effect transistors 有权
公开(公告)号：US20060258071A1
公开(公告)日：2006-11-16
申请号：US11490681
申请日：2006-07-21
申请人： Gurtej Sandhu , H. Manning , Cem Basceri
发明人： Gurtej Sandhu , H. Manning , Cem Basceri
IPC分类号： H01L21/337
CPC分类号： H01L29/66666 , H01L29/7827
摘要： A mass of material is formed over a semiconductor substrate. Semiconductive material is formed laterally proximate the mass of material. A space is provided laterally between the mass of material and the semiconductive material. The space comprises an outermost portion and a portion immediately adjacent thereto. The outermost portion has a maximum lateral width which is greater than that of the adjacent portion. Gate dielectric material and conductive gate material are formed within the space. The gate dielectric material and the conductive gate material in combination fill the adjacent portion of the space but do not fill the outermost portion of the space. At least the conductive gate material is etched from at least a majority of the outermost portion of the space. Source/drain regions are formed operatively proximate the conductive gate material and the semiconductive material is used as a channel region of the field effect transistor.

42. 发明申请

US20060051941A1 Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors 有权
标题翻译：形成包含外延硅的层的方法以及形成场效应晶体管的方法
公开(公告)号：US20060051941A1
公开(公告)日：2006-03-09
申请号：US11035298
申请日：2005-01-12
申请人： Eric Blomiley , Gurtej Sandhu , Cem Basceri , Nirmal Ramaswamy
发明人： Eric Blomiley , Gurtej Sandhu , Cem Basceri , Nirmal Ramaswamy
IPC分类号： H01L21/20
CPC分类号： H01L29/66787 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02642
摘要： The invention includes methods of forming layers comprising epitaxial silicon. In one implementation, an opening is formed within a first material received over a monocrystalline material. Opposing sidewalls of the opening are lined with a second material, with monocrystalline material being exposed at a base of the second material-lined opening. A silicon-comprising layer is epitaxially grown from the exposed monocrystalline material within the second material-lined opening. At least a portion of the second material lining is in situ removed. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成包含外延硅的层的方法。在一个实施方案中，在通过单晶材料接收的第一材料内形成开口。开口的相对侧壁衬有第二材料，其中单晶材料暴露在第二材料衬里开口的基部处。在第二材料衬里的开口内从暴露的单晶材料外延生长含硅层。第二材料衬里的至少一部分被原位去除。考虑了其他方面和实现。

43. 发明申请

US20060046618A1 Methods and systems for determining physical parameters of features on microfeature workpieces 审中-公开
标题翻译：用于确定微特征工件特征物理参数的方法和系统
公开(公告)号：US20060046618A1
公开(公告)日：2006-03-02
申请号：US10930307
申请日：2004-08-31
申请人： Gurtej Sandhu , Cem Basceri
发明人： Gurtej Sandhu , Cem Basceri
IPC分类号： B24B49/00
CPC分类号： B24B37/005 , B24B49/12
摘要： Methods and systems for determining physical parameters of features on microfeature workpieces. In one embodiment, a method includes directing a substantially coherent probe beam at a selected area of a feature on the microfeature workpiece to produce a reflected probe beam having phase information of different points within the selected area. The selected area can be only a portion of the workpiece. The method further includes determining a physical parameter of the feature at the different points within the selected area of the workpiece based on the reflected probe beam. The physical parameter can be a depth, height, thickness, width, or other dimension of a layer, trench, hole, projection, or other feature on the workpiece.
摘要翻译：用于确定微特征工件特征物理参数的方法和系统。在一个实施例中，一种方法包括将基本相干的探测光束引导到微特征工件上的特征的选定区域，以产生具有所选区域内的不同点的相位信息的反射探测光束。所选区域只能是工件的一部分。该方法还包括基于反射的探测光束在工件的选定区域内的不同点处确定特征的物理参数。物理参数可以是工件上的层，沟槽，孔，突起或其他特征的深度，高度，厚度，宽度或其他尺寸。

44. 发明申请

US20060046395A1 Forming a vertical transistor 有权
标题翻译：形成垂直晶体管
公开(公告)号：US20060046395A1
公开(公告)日：2006-03-02
申请号：US11256424
申请日：2005-10-20
申请人： Nirmal Ramaswamy , Gurtej Sandhu , Cem Basceri , Eric Blomiley
发明人： Nirmal Ramaswamy , Gurtej Sandhu , Cem Basceri , Eric Blomiley
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L29/66787 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L29/66553 , H01L29/66666 , H01L29/7827 , H01L29/78642
摘要： The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first portion of the monocrystalline material is outwardly exposed while a second portion of the monocrystalline material is masked. A first silicon-comprising layer is epitaxially grown from the exposed monocrystalline material of the first portion and not from the monocrystalline material of the masked second portion. After growing the first silicon-comprising layer, the second portion of the monocrystalline material is unmasked. A second silicon-comprising layer is then epitaxially grown from the first silicon-comprising layer and from the unmasked monocrystalline material of the second portion. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成外延含硅材料的方法和形成垂直晶体管的方法。在一个实施方案中，形成外延含硅材料的方法包括提供包括单晶材料的衬底。单晶材料的第一部分向外暴露，而单晶材料的第二部分被掩蔽。第一含硅层从第一部分的暴露的单晶材料而不是被掩蔽的第二部分的单晶材料外延生长。在生长第一含硅层之后，单晶材料的第二部分被未掩蔽。然后从第一含硅层和第二部分的未掩模的单晶材料外延生长第二含硅层。考虑了其他方面和实现。

45. 发明申请

US20060046392A1 Methods of forming vertical transistor structures 审中-公开
标题翻译：形成垂直晶体管结构的方法
公开(公告)号：US20060046392A1
公开(公告)日：2006-03-02
申请号：US10928467
申请日：2004-08-26
申请人： H. Manning , Kunal Parekh , Cem Basceri , Gurtej Sandhu
发明人： H. Manning , Kunal Parekh , Cem Basceri , Gurtej Sandhu
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/425 , H01L21/8242
CPC分类号： H01L29/66787 , H01L27/10808 , H01L27/10876
摘要： The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical transistor structure. Vertical transistor structures formed in accordance with methodology of the present invention can be incorporated into various types of integrated circuitry, including, for example, DRAM arrays.
摘要翻译：本发明包括这样的方法，其中使用成角度的注入来使源极/漏极区域注入与垂直晶体管结构的天线的顶部边缘自对准。本发明还包括其中使用成角度的植入物以在垂直晶体管结构的栅极下注入掺杂剂的方法。根据本发明的方法形成的垂直晶体管结构可以结合到各种类型的集成电路中，包括例如DRAM阵列。

46. 发明申请

US20060043448A1 Dielectric relaxation memory 有权
标题翻译：介质松弛记忆
公开(公告)号：US20060043448A1
公开(公告)日：2006-03-02
申请号：US10930774
申请日：2004-09-01
申请人： Cem Basceri , Gurtej Sandhu
发明人： Cem Basceri , Gurtej Sandhu
IPC分类号： H01L29/94
CPC分类号： H01L27/1085
摘要： A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as a memory device. A method of forming the trap cites involves an atomic layer deposition,of a material at pre-determined areas in the dielectric layer.
摘要翻译：一种具有设置在两个导电电极之间的电介质层的电容器结构，其中所述电介质层包含对应于特定能量状态的至少一个电荷陷阱位置。能量状态可以用于区分电容器结构的存储器状态，从而允许本发明用作存储器件。形成陷阱的方法涉及在电介质层中预定区域处的材料的原子层沉积。

47. 发明申请

US20050153551A1 Methods for deposition of semiconductor material 失效
标题翻译：半导体材料沉积方法
公开(公告)号：US20050153551A1
公开(公告)日：2005-07-14
申请号：US10755000
申请日：2004-01-09
申请人： Eric Blomiley , Gurtej Sandhu , Cem Basceri , Nirmal Ramaswamy
发明人： Eric Blomiley , Gurtej Sandhu , Cem Basceri , Nirmal Ramaswamy
IPC分类号： H01L21/20 , H01L21/205 , C30B1/00 , H01L21/302 , H01L21/36 , H01L21/461
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639
摘要： The invention includes a method for selective deposition of semiconductor material. A substrate is placed within a reaction chamber. The substrate comprises a first surface and a second surface. The first and second surfaces are exposed to a semiconductor material precursor under conditions in which growth of semiconductor material from the precursor comprises a lag phase prior to a growth phase, and under which it takes longer for the growth phase to initiate on the second surface than on the first surface. The exposure of the first and second surfaces is conducted for a time sufficient for the growth phase to occur on the first surface, but not long enough for the growth phase to occur on the second surface.
摘要翻译：本发明包括半导体材料的选择性沉积方法。将基板放置在反应室内。基板包括第一表面和第二表面。第一表面和第二表面在半导体材料前体暴露于其中来自前体的半导体材料的生长在生长阶段之前包含滞后期的条件下，并且在该阶段生长阶段在第二表面上开始需要更长时间比在第一个表面。进行第一表面和第二表面的曝光足够长的时间，以使生长阶段在第一表面上发生，但是不足以使生长相发生在第二表面上。

48. 发明授权

US06917112B2 Conductive semiconductor structures containing metal oxide regions 失效
标题翻译：含有金属氧化物区域的导电半导体结构
公开(公告)号：US06917112B2
公开(公告)日：2005-07-12
申请号：US10227662
申请日：2002-08-26
申请人： Cem Basceri , Gurtej Sandhu
发明人： Cem Basceri , Gurtej Sandhu
IPC分类号： H01L21/02 , H01L21/768 , H01L23/48
CPC分类号： H01L28/75 , H01L21/76888 , H01L28/55 , H01L28/84
摘要： A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g.. ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boundaries of the metal layer, e.g., platinum, to oxidize a metal layer thereon, e.g, ruthenium layer. The structure is particularly advantageous for use in capacitor structures and memory devices, such as dynamic random access memory (DRAM) devices.
摘要翻译：一种用于形成金属/金属氧化物结构的方法，其包括在金属层例如铂的晶界处形成金属氧化物区域，例如氧化钌区域。优选地，金属氧化物区域通过氧气通过金属层例如铂的晶界的扩散而形成，以氧化其上的金属层，例如钌层。该结构对于用于诸如动态随机存取存储器（DRAM）器件的电容器结构和存储器件尤为有利。

49. 发明申请

US20050079697A1 Plasma enhanced chemical vapor deposition method of forming a titanium silicide comprising layer 有权
标题翻译：形成层状硅化钛的等离子体增强化学气相沉积法
公开(公告)号：US20050079697A1
公开(公告)日：2005-04-14
申请号：US10666025
申请日：2003-09-17
申请人： Cem Basceri , Irina Vasilyeva , Ammar Derraa , Philip Campbell , Gurtej Sandhu
发明人： Cem Basceri , Irina Vasilyeva , Ammar Derraa , Philip Campbell , Gurtej Sandhu
IPC分类号： C23C16/42 , H01L21/285 , H01L21/44
CPC分类号： H01L21/28518 , C23C16/42 , H01L21/28556
摘要： Chemical vapor deposition methods of forming titanium silicide including layers on substrates are disclosed. TiCl4 and at least one silane are first fed to the chamber at or above a first volumetric ratio of TiCl4 to silane for a first period of time. The ratio is sufficiently high to avoid measurable deposition of titanium silicide on the substrate. Alternately, no measurable silane is fed to the chamber for a first period of time. Regardless, after the first period, TiCl4 and at least one silane are fed to the chamber at or below a second volumetric ratio of TiCl4 to silane for a second period of time. If at least one silane was fed during the first period of time, the second volumetric ratio is lower than the first volumetric ratio. Regardless, the second feeding is effective to plasma enhance chemical vapor deposit a titanium silicide including layer on the substrate.
摘要翻译：公开了在衬底上形成包括层的硅化钛的化学气相沉积方法。首先将TiCl 4和至少一种硅烷以等于或高于TiCl 4与硅烷的第一体积比在第一时间段内进料至室。该比例足够高以避免钛硅化物在衬底上的可测量沉积。或者，在第一时间段内没有可测量的硅烷进料到室中。无论如何，在第一阶段之后，将TiCl 4和至少一种硅烷以等于或低于第二体积比的TiCl 4与硅烷进料至室中第二时间段。如果在第一时间段内进料至少一种硅烷，则第二体积比率低于第一体积比。无论如何，第二次进料对于等离子体有效地提高了化学气相沉积在基底上的包含硅的硅化钛。

50. 发明授权

US07444934B2 Supercritical fluid-assisted direct write for printing integrated circuits 失效
标题翻译：用于印刷集成电路的超临界流体辅助直接写入
公开(公告)号：US07444934B2
公开(公告)日：2008-11-04
申请号：US11135453
申请日：2005-05-24
申请人： Gurtej Sandhu , Cem Basceri
发明人： Gurtej Sandhu , Cem Basceri
IPC分类号： B41F33/00
CPC分类号： B41F33/00 , B33Y40/00 , H01L21/288 , H01L21/76838 , H01L23/5328 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： High resolution patterns provided on a surface of a semiconductor substrate and methods of direct printing of such high resolution patterns are disclosed. The high resolution patterns may have dimensions less than 0.1 micron and are formed by a direct writing method employing a supercritical fluid comprising nanometer-sized particles, which may be optionally electrically charged.
摘要翻译：公开了在半导体衬底的表面上提供的高分辨率图案以及直接印刷这种高分辨率图案的方法。高分辨率图案可以具有小于0.1微米的尺寸，并且通过使用包含纳米尺寸颗粒的超临界流体的直接书写方法形成，所述超临界流体可以任选带电。

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