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    • 42. 发明授权
    • Pulse radar receiver
    • 脉冲雷达接收机
    • US08754806B2
    • 2014-06-17
    • US13316381
    • 2011-12-09
    • Pil Jae ParkSeong Do KimSung Chul WooHyun Kyu Yu
    • Pil Jae ParkSeong Do KimSung Chul WooHyun Kyu Yu
    • G01S7/285G01S7/00G01S13/10
    • G01S7/292
    • A pulse radar receiver includes a power splitter configured to split a transmit (TX) trigger signal for generating a TX pulse, a phase-locked loop (PLL) configured to receive a division ratio and the TX trigger signal split by the power splitter, and generate a sampling frequency, and a sampler configured to sample a reflected wave received through an RX antenna, according to the sampling frequency generated by the PLL. Accordingly, it is possible to provide a high distance resolution by generating a sampling frequency with a difference from a TX pulse to sample a reflected wave received through an RX antenna. Thus, it is possible to overcome a limitation in the distance resolution due to the pulse width and to measure a minute movement at a short distance. Therefore, the pulse radar receiver is applicable to high range resolution radar applications such as a living body measuring radar.
    • 脉冲雷达接收机包括:功率分配器,被配置为分离用于产生TX脉冲的发射(TX)触发信号;配置为接收分频比的锁相环(PLL)和由功率分配器分离的TX触发信号;以及 产生采样频率,并且采样器被配置为根据由PLL产生的采样频率对通过RX天线接收的反射波进行采样。 因此,通过产生与TX脉冲不同的采样频率来采样通过RX天线接收的反射波,可以提供高距离分辨率。 因此,可以克服由于脉冲宽度导致的距离分辨率的限制并且能够在短距离处测量微小的移动。 因此,脉冲雷达接收机适用于诸如生物体测量雷达的高范围分辨率雷达应用。
    • 47. 发明授权
    • Time-to-digital converter and all digital phase-locked loop including the same
    • 时间到数字转换器和所有数字锁相环包括相同的
    • US08344772B2
    • 2013-01-01
    • US12956498
    • 2010-11-30
    • Ja Yol LeeSeon Ho HanMi Jeong ParkJang Hong ChoiSeong Do KimHyun Kyu Yu
    • Ja Yol LeeSeon Ho HanMi Jeong ParkJang Hong ChoiSeong Do KimHyun Kyu Yu
    • H03L7/06
    • H03L7/095G04F10/005H03L7/085H03L7/103H03L2207/50
    • An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.
    • 全数字锁相环(ADPLL)包括:相位计数器累积频率设定字值和数字控制振荡器(DCO)时钟的相位,并检测参考时钟和重新定时钟之间的精细相位差; 相位检测器,根据所述精细相位差检测补偿所述频率设定字值与所述DCO时钟之间的相位差的数字相位误差值,以检测数字相位误差值; 数字环路滤波器滤除数字相位误差值并控制PLL的操作特性; 锁定检测器,根据数字环路滤波器的输出产生锁定指示信号; 数字控制振荡器根据数字环路滤波器的输出改变DCO时钟的频率; 以及重新计时的时钟发生器,通过以低频再定时DCO时钟产生重定时钟。
    • 48. 发明授权
    • Wideband receiver
    • 宽带接收机
    • US08306498B2
    • 2012-11-06
    • US12970874
    • 2010-12-16
    • Hyun Kyu YuJoon Hee LeeSeong Hwan Cho
    • Hyun Kyu YuJoon Hee LeeSeong Hwan Cho
    • H04B1/18H04K3/00
    • H04B1/28H03D7/1441H03D7/1458
    • Provided is a wideband receiver that has a smaller area and consumes less power and can prevent harmonic mixing occurring due to an increase in the number of communications systems using wideband. A wideband receiver according to an aspect of the invention may include: an front-end unit receiving and performing low-pass filtering on a wideband input signal in a continuous-time domain; and a down-conversion unit sampling and holding an output signal of the front-end unit according to a local oscillator signal and performing low-pass filtering on the output signal in a discrete tie domain.
    • 提供了一种宽带接收机,其具有较小的面积并且消耗更少的功率,并且可以防止由于使用宽带的通信系统的数量的增加而发生谐波混合。 根据本发明的一个方面的宽带接收机可以包括:前端单元在连续时域中接收并对宽带输入信号执行低通滤波; 下变频单元根据本地振荡器信号对前端单元的输出信号进行采样和保持,并对离散的连接域中的输出信号进行低通滤波。