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41. 发明授权

US07502216B2 Multilayer chip capacitor 有权
标题翻译：多层片式电容器
公开(公告)号：US07502216B2
公开(公告)日：2009-03-10
申请号：US12010018
申请日：2008-01-18
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228
CPC分类号： H01G4/232 , H01G4/012 , H01G4/30
摘要： A multilayer chip capacitor includes: a capacitor body; internal electrodes disposed in the capacitor body, each internal electrode having one or more lead; and external electrodes disposed on first and second side surfaces of the capacitor body to be electrically connected to the internal electrodes through the leads. The average number of leads in each internal electrode is smaller than half (½) of the total number of external electrodes. The leads of the internal electrodes having opposite polarities and adjacent in the lamination direction are disposed to be adjacent to each other as seen from the lamination direction. All the internal electrodes having the same polarity are electrically connected to each other in the capacitor.
摘要翻译：多层片状电容器包括：电容器本体; 设置在电容器本体中的内部电极，每个内部电极具有一个或多个引线; 以及设置在电容器主体的第一和第二侧面上的外部电极，以通过引线与内部电极电连接。每个内部电极的引线平均数小于外部电极总数的一半（1/2）。具有相反极性并且在层叠方向上相邻的内部电极的引线设置成从层叠方向看彼此相邻。具有相同极性的所有内部电极在电容器中彼此电连接。

42. 发明申请

US20080310078A1 Method of implementing low ESL and controlled ESR of multilayer capacitor 有权
标题翻译：实现低ESL和多层电容控制ESR的方法
公开(公告)号：US20080310078A1
公开(公告)日：2008-12-18
申请号：US12155805
申请日：2008-06-10
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/232
CPC分类号： H01G4/232 , H01G4/30
摘要： Disclosed is a method of implementing controlled equivalent series resistance (ESR) having low equivalent series inductance (ESL) of a multi-layer chip capacitor which includes a plurality of internal electrodes each having first polarity or second polarity which is opposite to the first polarity, and dielectric layers each disposed between the internal electrodes of the first polarity and the second polarity, wherein the internal electrodes having the first polarity and the internal electrodes having the second polarity are alternated at least once to form one or more blocks being stacked.
摘要翻译：公开了一种实现具有低等效串联电感（ESL）的受控等效串联电阻（ESR）的方法，该多层片式电容器包括多个内部电极，每个内部电极具有与第一极性相反的第一极性或第二极性，以及介电层，其各自设置在第一极性和第二极性的内部电极之间，其中具有第一极性的内部电极和具有第二极性的内部电极至少交替一次以形成一个或多个堆叠的块。

43. 发明授权

US08159813B2 Multilayer chip capacitor, motherboard apparatus having the same, and power distribution network 有权
标题翻译：多层片式电容器，具有相同的主板设备和配电网络
公开(公告)号：US08159813B2
公开(公告)日：2012-04-17
申请号：US12270330
申请日：2008-11-13
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/005 , H01G4/06
CPC分类号： H01G4/385 , H01G4/005 , H01G4/30 , H01L2224/16227 , H01L2924/15311 , H01L2924/19105
摘要： There is provided a multilayer chip capacitor including: a capacitor body including first and second capacitor units arranged in a laminated direction; and first to fourth outer electrodes formed on side surfaces of the capacitor body, respectively, wherein the first capacitor unit includes first and second inner electrodes of different polarities alternately arranged in the capacitor body to oppose each other while interposing a corresponding one of dielectric layers, the second capacitor unit includes third and fourth inner electrodes of different polarities alternately arranged in the capacitor body to oppose each other while interposing another corresponding one of the dielectric layers, the first and second capacitor units are electrically insulated from each other, and the first capacitor unit operates in a first frequency range and the second capacitor unit operates in a second frequency range lower than the first frequency range.
摘要翻译：提供了一种多层片状电容器，包括：电容器体，包括沿层叠方向布置的第一和第二电容器单元; 以及分别形成在电容器主体的侧面上的第一至第四外部电极，其中，所述第一电容器单元包括交替布置在所述电容器体中的第一和第二内部电极，所述第一和第二内部电极彼此相对，同时插入相应的一个电介质层，所述第二电容器单元包括具有不同极性的第三和第四内部电极，所述第三和第四内部电极交替地布置在所述电容器体中，以相对于彼此相对，同时插入另一个对应的一个所述介电层，所述第一和第二电容器单元彼此电绝缘，单元在第一频率范围内操作，并且第二电容器单元在低于第一频率范围的第二频率范围内操作。

44. 发明申请

US20100238605A1 MULTILAYER CHIP CAPACITOR AND METHOD OF FABRICATING THE SAME 有权
标题翻译：多层芯片电容器及其制造方法
公开(公告)号：US20100238605A1
公开(公告)日：2010-09-23
申请号：US12650134
申请日：2009-12-30
申请人： Byoung Hwa LEE , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa LEE , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228
CPC分类号： H01G4/232 , H01G2/065 , H01G4/30 , H05K1/0231 , H05K1/0295 , H05K1/181 , H05K2201/0979 , H05K2201/09954 , Y10T29/435
摘要： A multilayer chip capacitor includes: a capacitor main body; a plurality of first and second inner electrodes; and m (m≧3) number of first and second outer electrodes. The plurality of first and second inner electrodes are connected with two outer electrodes positioned on both opposing surfaces and having the same polarity as that of the first and second inner electrodes, and classified into a plurality of groups depending on the locations of the outer electrodes connected to the first and second inner electrodes. At least one of two outer electrodes connected with inner electrodes of each group is different from an outer electrode connected with inner electrodes of a different group having the same polarity, and inner electrodes of one group are connected to outer electrodes connected with at least another one group so that all the inner electrodes belonging to the same polarity can be electrically connected.
摘要翻译：一种多层片状电容器包括：电容器主体; 多个第一和第二内部电极; 和m（m≥3）个数的第一和第二外部电极。多个第一和第二内部电极与位于两个相对表面上并且具有与第一和第二内部电极相同的极性的两个外部电极连接，并且根据连接的外部电极的位置被分成多个组到第一和第二内部电极。与每组的内部电极连接的两个外部电极中的至少一个不同于与具有相同极性的不同组的内部电极连接的外部电极，并且一组的内部电极连接到与至少另一个连接的外部电极使得属于相同极性的所有内部电极可以电连接。

45. 发明授权

US07688568B1 Multilayer chip capacitor 有权
标题翻译：多层片式电容器
公开(公告)号：US07688568B1
公开(公告)日：2010-03-30
申请号：US12407298
申请日：2009-03-19
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hong Yeon Cho , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hong Yeon Cho , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228
CPC分类号： H01G4/30 , H01G4/232 , H01G4/385 , H01L2224/16227 , H01L2924/15311
摘要： A multilayer chip capacitor includes: a capacitor body having a plurality of dielectric layers laminated therein and comprising first and second capacitor units; and first to fourth external electrodes formed on an outer surface of the capacitor body, wherein the first capacitor unit comprises first and second internal electrodes facing each other with the dielectric layer interposed therebetween, connected to the first and second external electrodes, and having different polarities, each pair of first and second internal electrodes being laminated one or more times to discriminate a plurality of capacitors with a certain capacitance, the second capacitor unit comprises third and fourth internal electrodes facing each other with the dielectric layer interposed therebetween, connected to the third and fourth external electrodes, and having the same polarities as those of the first and second internal electrodes, each pair of third and fourth internal electrodes being laminated one or more times to discriminate one or more capacitors each with a certain capacitance, and at least three capacitors included in the first and second capacitor units have different capacitances or resonance frequencies.
摘要翻译：一种多层片状电容器包括：电容器主体，其具有层叠在其中的多个电介质层，并且包括第一和第二电容器单元; 以及形成在所述电容器主体的外表面上的第一至第四外部电极，其中所述第一电容器单元包括彼此面对的第一和第二内部电极，所述电介质层插入在所述第一和第二内部电极之间，连接到所述第一和第二外部电极，并具有不同的极性每一对第一和第二内部电极层叠一次或多次以区分具有一定电容的多个电容器，第二电容器单元包括彼此面对的第三和第四内部电极，介电层插入其间，连接到第三个和第四外部电极，并且具有与第一和第二内部电极相同的极性，每对第三和第四内部电极被层叠一次或多次以区分一个或多个具有一定电容的电容器，并且至少三个电容器包括在第一和第二电容器单元ha中不同的电容或谐振频率。

46. 发明授权

US07679882B2 Multilayered chip capacitor and capacitance tunning method of the same 失效
标题翻译：多层片式电容器和电容调谐方法相同
公开(公告)号：US07679882B2
公开(公告)日：2010-03-16
申请号：US12238688
申请日：2008-09-26
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228
CPC分类号： H01G4/228 , H01G4/005 , H01G4/30 , H01G4/385
摘要： There is provided a multilayer chip capacitor capable of tuning capacitance, including: a capacitor body where a plurality of dielectric layers are laminated; a plurality of pairs of first and second internal electrodes arranged alternately, while interposing a corresponding one of the dielectric layers; and a plurality of pairs of first and second external electrodes connected to the first and second internal electrodes, wherein the first and second internal electrodes include a plurality of groups each including at least one pair of the first and second internal electrodes, and the first and second internal electrodes of each of the groups are connected to different pairs of the first and second external electrodes, respectively, wherein a corresponding one of the pairs of the first and second external electrodes is selectively connected to power lines so that the multilayer chip capacitor has at least two different capacitances.
摘要翻译：提供一种能够调谐电容的多层片状电容器，包括：电容器体，层叠多个电介质层; 多个成对的第一和第二内部电极交替布置，同时插入相应的一个电介质层; 以及连接到所述第一和第二内部电极的多对第一和第二外部电极，其中所述第一和第二内部电极包括多个组，每个组包括至少一对所述第一和第二内部电极，以及所述第一和第二内部电极每个组的第二内部电极分别连接到第一和第二外部电极的不同对，其中第一和第二外部电极对中的相应一个选择性地连接到电力线，使得多层片状电容器具有至少两个不同的电容。

47. 发明授权

US07675733B2 Multilayer capacitor 有权
标题翻译：多层电容器
公开(公告)号：US07675733B2
公开(公告)日：2010-03-09
申请号：US12237837
申请日：2008-09-25
申请人： Byoung Hwa Lee , Sung Kwon Wi , Sang Soo Park , Min Cheol Park , Dong Seok Park , Hae Suk Chung
发明人： Byoung Hwa Lee , Sung Kwon Wi , Sang Soo Park , Min Cheol Park , Dong Seok Park , Hae Suk Chung
IPC分类号： H01G4/228
CPC分类号： H01G4/232 , H01G4/012 , H01G4/30
摘要： There is provided a multilayer capacitor including an inner connecting conductor of at least one polarity; a plurality of first and second outer electrodes formed on a surface of the body, wherein the inner connecting conductor is connected to a corresponding one of the outer electrodes having identical polarity, a corresponding one of the inner electrodes having identical polarity to the inner connecting conductor includes a plurality of groups each including at least one of the inner electrodes, wherein the inner electrodes of the respective groups are connected to the outer electrodes having identical polarity that are different from one another for each of the groups and electrically connected to the inner connecting conductor through the connected outer electrode.
摘要翻译：提供一种包括至少一个极性的内连接导体的多层电容器; 形成在所述主体的表面上的多个第一和第二外部电极，其中所述内部连接导体连接到具有相同极性的对应的一个外部电极，相应的一个所述内部电极具有与所述内部连接导体包括多个组，每个组包括至少一个内部电极，其中各组的内部电极连接到具有与每个组相互不同的极性相同的外部电极，并且电连接到内部连接导体通过连接的外部电极。

48. 发明申请

US20090279228A1 MULTILAYER CHIP CAPACITOR 有权
标题翻译：多层芯片电容器
公开(公告)号：US20090279228A1
公开(公告)日：2009-11-12
申请号：US12267112
申请日：2008-11-07
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/30
CPC分类号： H01G4/30 , H01G4/012 , H01G4/232
摘要： A multilayer chip capacitor includes a capacitor body provided by a stack of a plurality of dielectric layers, a plurality of internal electrodes disposed in the capacitor body such that the internal electrodes of opposite polarities are alternately disposed to face each other with the dielectric layer interposed between each facing set of the internal electrodes, and a plurality of external electrodes disposed on an outer face of the capacitor body and electrically connected with the internal electrode. Each of the plurality of internal electrodes includes a main electrode part, and at least one lead extending from the main electrode part to a side face of the capacitor body and connected to a corresponding one of the external electrodes. The lead extends to the corresponding external electrode to be inclined with respect to the main electrode part thereof.
摘要翻译：多层片状电容器包括：由多个电介质层的堆叠体构成的电容器主体，设置在电容器主体中的多个内部电极，使得相互极性的内部电极交替地配置成彼此面对，其中介电层介于每个面对的内部电极组，以及多个外部电极，设置在电容器主体的外表面上并与内部电极电连接。多个内部电极中的每一个包括主电极部分和从电极主体的主电极部分延伸到侧面的至少一个引线，并连接到对应的一个外部电极。引线延伸到对应的外部电极，以相对于其主电极部分倾斜。

49. 发明授权

US07599166B2 Multilayer chip capacitor 有权
标题翻译：多层片式电容器
公开(公告)号：US07599166B2
公开(公告)日：2009-10-06
申请号：US11598672
申请日：2006-11-14
申请人： Byoung Hwa Lee , Hae Suk Chung , Dong Seok Park , Min Cheol Park , Sang Soo Park , Sung Kwon Wi
发明人： Byoung Hwa Lee , Hae Suk Chung , Dong Seok Park , Min Cheol Park , Sang Soo Park , Sung Kwon Wi
IPC分类号： H01G4/00 , H01G4/005
CPC分类号： H01G4/30 , H01G4/012 , H01G4/232
摘要： A multilayer chip capacitor includes a capacitor body having dielectric layers, and internal electrode layers separated from each other in the capacitor body by the dielectric layers. Each internal electrode layer has one or two leads and includes at least one coplanar electrode plate. External electrodes are electrically connected to the internal electrode layers via the leads. The internal electrode layers constitute a plurality of blocks stacked repeatedly. Each block includes a plurality of the internal electrode layers stacked successively. The leads extending to a face of the capacitor body are arranged in a zigzag shape along a stacking direction. The leads of vertically adjacent ones of the electrode plates having opposite polarities are arranged to be horizontally adjacent to each other.
摘要翻译：多层片状电容器包括具有电介质层的电容器主体，以及通过电介质层在电容器主体中彼此分离的内部电极层。每个内部电极层具有一个或两个引线并且包括至少一个共面电极板。外部电极通过引线电连接到内部电极层。内部电极层构成反复堆叠的多个块。每个块包括依次层叠的多个内部电极层。延伸到电容器主体的表面的引线沿堆叠方向布置成Z字形。具有相反极性的垂直相邻电极板的引线被布置成水平相邻。

50. 发明授权

US07595973B1 Multilayer chip capacitor and circuit board apparatus having the capacitor 有权
标题翻译：具有电容器的多层片状电容器和电路板装置
公开(公告)号：US07595973B1
公开(公告)日：2009-09-29
申请号：US12262909
申请日：2008-10-31
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228
CPC分类号： H01G4/232 , H01G4/005 , H01G4/30 , H05K1/0231 , H05K1/113 , H05K2201/10636 , Y02P70/611
摘要： There is provided a multilayer chip capacitor including: a capacitor body including first and second capacitor units disposed in a laminated direction; first to fourth outer electrodes formed on side surfaces of the capacitor body, respectively; and at least one connecting conductor line connecting the first and third outer electrodes having identical polarity to each other and the second and fourth outer electrodes having identical polarity to each other, wherein the first capacitor body includes first and second inner electrodes, the second capacitor unit includes a plurality of third and fourth inner electrodes, the first to fourth outer electrodes are connected to the first to fourth inner electrodes, respectively, and an equivalent series resistance (R1) of the first capacitor unit and a combined equivalent series resistance (R2′) of the second capacitor and the connecting conductor line satisfy the Equation 0.7(R1)≦R2′≦1.3(R1).
摘要翻译：提供了一种多层片状电容器，包括：电容器主体，包括沿层叠方向设置的第一和第二电容器单元; 分别形成在电容器主体的侧表面上的第一至第四外部电极; 以及连接第一和第三外部电极的至少一个连接导线，彼此具有相同的极性，第二和第四外部电极彼此具有相同的极性，其中第一电容器主体包括第一和第二内部电极，第二电容器单元包括多个第三和第四内部电极，第一至第四外部电极分别连接到第一至第四内部电极，并且第一电容器单元的等效串联电阻（R1）和组合的等效串联电阻（R2' ）和连接导线满足公式0.7（R1）<= R2'<= 1.3（R1）。

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