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41. 发明授权

US07360063B2 Method for SIMD-oriented management of register maps for map-based indirect register-file access 有权
标题翻译：用于基于地图的间接寄存器文件访问的用于面向SIMD管理寄存器映射的方法
公开(公告)号：US07360063B2
公开(公告)日：2008-04-15
申请号：US11366884
申请日：2006-03-02
申请人： Peter G. Capek , Jeffrey H. Derby , Robert K. Montoye
发明人： Peter G. Capek , Jeffrey H. Derby , Robert K. Montoye
IPC分类号： G06F9/35
CPC分类号： G06F9/3012 , G06F9/3004 , G06F9/30098 , G06F9/3013 , G06F9/30138 , G06F9/30145 , G06F9/30167 , G06F9/35 , G06F9/384
摘要： A facility is provided for managing register maps for map-based indirect register file access within a processor. The management facility includes a register mapping including a set of maps, each map of the set of maps having a plurality of map registers. A set of actual registers is indirectly accessed by the processor via map entries of the set of maps. The number of actual registers in the set of actual registers is greater than the number of map entries in the set of maps, and the map entries of the set of maps reference only a subset of the set of actual registers at any given time. The facility includes managing updates to multiple entries of the set of maps of the register mapping by updating multiple map entries of at least one map of the set of maps responsive to executing a single update instruction.
摘要翻译：提供了一种用于管理处理器内基于地图的间接寄存器文件访问的寄存器映射的设施。管理设施包括包括一组映射的寄存器映射，该映射集合的每个映射具有多个映射寄存器。一组实际寄存器由处理器通过地图集的映射条目间接访问。实际寄存器组中实际寄存器的数量大于映射集中映射条目的数量，映射集合的映射条目仅引用任何给定时间的实际寄存器集合的子集。该设施包括通过基于执行单个更新指令来更新该组映射的至少一个映射的多个映射条目来管理对该映射映射集合的多个条目的更新。

42. 发明授权

US07216141B2 Computing carry-in bit to most significant bit carry save adder in current stage 失效
标题翻译：计算进位位到当前阶段的最高有效位进位保存加法器
公开(公告)号：US07216141B2
公开(公告)日：2007-05-08
申请号：US10702992
申请日：2003-11-06
申请人： Wendy A. Belluomini , Ramyanshu Datta , Jente Benedict Kuang , Chandler T. McDowell , Robert K. Montoye , Hung C. Ngo
发明人： Wendy A. Belluomini , Ramyanshu Datta , Jente Benedict Kuang , Chandler T. McDowell , Robert K. Montoye , Hung C. Ngo
IPC分类号： G06F7/50
CPC分类号： G06F7/607
摘要： A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.
摘要翻译：一个4对2进位存储加法器，减少输出和输入位的延迟。 4对2进位存储加法器可以包括耦合到较高阶全加器的较低阶满载。进位保存加法器还可以包括耦合到高阶全加器的逻辑单元，其中逻辑单元被配置为产生要输入到通常将从位于该位置的进位保存加法器产生的高阶全加器的进位位前一阶段通过在当前阶段而不是在前一阶段生成该进位位（进位位），减少输入到较高阶全加器的进位位的延迟，从而减少输出和和输出位的延迟由高阶全加器。

43. 发明授权

US5266849A Tri state buffer circuit for dual power system 失效
标题翻译：用于双电源系统的三态缓冲电路
公开(公告)号：US5266849A
公开(公告)日：1993-11-30
申请号：US839480
申请日：1992-02-19
申请人： Takeshi Kitahara , Robert K. Montoye
发明人： Takeshi Kitahara , Robert K. Montoye
IPC分类号： H03K19/0175 , H03K19/003 , H03K19/0185 , H03K19/094 , H03K19/00
CPC分类号： H03K19/00315 , H03K19/018514 , H03K19/09429
摘要： A CMOS tri-state buffer circuit transfers digital signals between a first digital circuit system operating at 3.3 Volts and a second system operating at 5 Volts. The buffer circuit receives an active high enable signal and a data signal as inputs to a tri-state select network. When the enable signal is high, data is propagated through a driver stage and onto a data bus in the second system. Driver clamp circuitry and an n-well voltage controller operate conjunction with the driver stage to prevent the 5 volt supply of the second system from interfering with the circuitry of the of the 3.3 Volt system. A clamped line driver transmits signals from the 5 Volt system to the 3.3 Volt system.
摘要翻译： CMOS三态缓冲电路在工作在3.3伏特的第一数字电路系统和以5伏特操作的第二个系统之间传输数字信号。缓冲电路接收有效的高使能信号和作为三态选择网络的输入的数据信号。当使能信号为高电平时，数据通过驱动级传播到第二系统的数据总线上。驱动器钳位电路和n阱电压控制器与驱动器级联运行，以防止第二个系统的5伏电源干扰3.3伏特系统的电路。钳位线驱动器将信号从5伏系统传输到3.3伏特系统。

44. 发明授权

US4969118A Floating point unit for calculating A=XY+Z having simultaneous multiply and add 失效
标题翻译：用于计算A = XY + Z的浮点单元，具有同时乘法和加法
公开(公告)号：US4969118A
公开(公告)日：1990-11-06
申请号：US297016
申请日：1989-01-13
申请人： Robert K. Montoye , John Cocke
发明人： Robert K. Montoye , John Cocke
IPC分类号： G06F7/487 , G06F7/527 , G06F7/53 , G06F7/544
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/49936 , G06F7/49947
摘要： A single floating point that produces the result A.times.B+C with A, B and C being floating point numbers. The operand C is shifted in parallel with the beginning phases of the multiplication. The result is produced after a single addition and normalization, reducing hardware, delay and rounding errors.

45. 发明授权

US4926369A Leading 0/1 anticipator (LZA) 失效
标题翻译：领先0/1预期者（LZA）
公开(公告)号：US4926369A
公开(公告)日：1990-05-15
申请号：US255089
申请日：1988-10-07
申请人： Erdem Hokenek , Robert K. Montoye
发明人： Erdem Hokenek , Robert K. Montoye
IPC分类号： G06F7/485 , G06F5/01 , G06F7/00 , G06F7/508 , G06F7/74
CPC分类号： G06F7/74 , G06F5/012
摘要： A method and system for performing a leading 0/1 anticipation (LZA) in parallel with the floating-point addition of two operands (A and B) in a computer to significantly reduce the Addition-Normalization time. A combinational network is used to process appropriate XOR (P), AND (G) and NOR (Z) state signals resulting from the comparison of the bits in corresponding bit positions of the operands (A and B), starting with the most significant bit (MSB) side of the addition. The state of the initial state signal is detected and shift amount signals are produced and counted for each successive state signal detected, as long as the state remains TRUE. When the state becomes NOT TRUE, adjustments are made depending on the initial state and the successive state, and production of the shift amount signals is halted and an adjustment signal is produced. To determine the exponent of the sum of the floating-point addition, the shift amount count is summed with the adjustment signal. The latter sum will be the exponent of the sum of the operands thus providing a normalized result. The adjustment signal may be based on the CARRY at the NOT TRUE bit position, and the state at the NOT TRUE position may be used to determine whether the result of the addition is positive or negative. In addition to a serial network, an implementing network of a parallel form which accepts appropriate state inputs as blocks of n bits in length, is disclosed, along with certain special implementations.

46. 发明授权

US09093151B2 Programmable regular expression and context free grammar matcher 有权
标题翻译：可编程正则表达式和上下文无关语法匹配器
公开(公告)号：US09093151B2
公开(公告)日：2015-07-28
申请号：US13495535
申请日：2012-06-13
申请人： Richard F. Freitas , Robert K. Montoye , Rajendra Shinde
发明人： Richard F. Freitas , Robert K. Montoye , Rajendra Shinde
IPC分类号： G06F17/27 , G11C15/04 , G11C13/00
CPC分类号： G11C15/046 , G11C13/0004
摘要： A regular expression matcher system, including: a deterministic finite state machine (DFSM); a ternary content addressable memory (TCAM) matcher to compare a word stored at the TCAM matcher to an input stream, wherein the word determines a state-to-state transition of the DFSM from a comparison result; a programmable logic connected to an output of the TCAM matcher to identify a next state in the DFSM based on the comparison result; a state register to update a current state of the DFSM to the next state; and a collection data structure coupled to the TCAM matcher and the programmable logic to store a sequence of required state transitions for the DFSM, wherein the programmable logic determines a next required state transition to be matched from the sequence.
摘要翻译：正则表达式匹配器系统，包括：确定性有限状态机（DFSM）; 三进制内容可寻址存储器（TCAM）匹配器，用于将存储在TCAM匹配器中的字与输入流进行比较，其中该字从比较结果确定DFSM的状态到状态转换; 连接到TCAM匹配器的输出的可编程逻辑基于比较结果识别DFSM中的下一状态; 状态寄存器，用于将DFSM的当前状态更新为下一状态; 以及耦合到所述TCAM匹配器和所述可编程逻辑以存储所述DFSM的所需状态转换序列的收集数据结构，其中所述可编程逻辑确定要从所述序列匹配的下一个所需状态转换。

47. 发明授权

US08918623B2 Implementing instruction set architectures with non-contiguous register file specifiers 有权
标题翻译：用不连续的寄存器文件说明符来实现指令集体系结构
公开(公告)号：US08918623B2
公开(公告)日：2014-12-23
申请号：US13425808
申请日：2012-03-21
申请人： Michael Karl Gschwind , Robert K. Montoye , Brett Olsson , John-David Wellman
发明人： Michael Karl Gschwind , Robert K. Montoye , Brett Olsson , John-David Wellman
IPC分类号： G06F9/30
CPC分类号： G06F9/30185 , G06F9/30032 , G06F9/30036 , G06F9/30105 , G06F9/30138 , G06F9/3016 , G06F9/30181
摘要： There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing an instruction of an instruction set using a non-contiguous register specifier of a non-contiguous register specification. The instruction includes the non-contiguous register specifier.
摘要翻译：提供了用于实现具有非连续寄存器文件说明符的指令集架构的方法和计算机程序产品。一种用于处理指令代码的方法包括使用非连续寄存器规范的非连续寄存器说明符来处理指令集的指令。该指令包括不连续的寄存器说明符。

48. 发明授权

US08661072B2 Shared parallel adder tree for executing multiple different population count operations 失效
标题翻译：共享并行加法器树，用于执行多个不同的群体计数操作
公开(公告)号：US08661072B2
公开(公告)日：2014-02-25
申请号：US12193782
申请日：2008-08-19
申请人： Bartholomew Blaner , Todd R. Iglehart , Robert K. Montoye
发明人： Bartholomew Blaner , Todd R. Iglehart , Robert K. Montoye
IPC分类号： G06F7/50
CPC分类号： G06F7/505
摘要： A shared parallel adder tree for executing multiple different population count operations on a single datum includes a number of carry-save adders (CSAs) and/or half adders (HAs), arranged in rows, where certain CSAs and HAs are dedicated to a single population count operation, while other CSAs and HAs are shared among two or more population count operations. The datum is applied to the first row in the tree. Partial sums of the number of ones at various locations within the tree are routed to certain CSAs and/or HAs “down” the tree to propagate the particular population count operations. Carry-propagate adders generate at least a portion of the final sum of the number of ones in certain population count operations. An “AND” operation on a particular number of the bits in the datum provides the high order bit of the resulting sum of the particular population count operation.
摘要翻译：用于在单个数据上执行多个不同总体计数操作的共享并行加法器树包括排列成行的多个进位保存加法器（CSA）和/或半加法器（HA），其中某些CSA和HA专用于单个人口计数操作，而其他CSA和HA在两个或多个人口计数操作之间共享。基准应用于树中的第一行。树中不同位置处的数量的部分和被路由到特定的CSA和/或HAs“树”，以传播特定的群体计数操作。携带传播加法器产生某些人口计数操作中的数量的最后总和的至少一部分。数据中特定位数的“与”运算提供特定总体计数操作的结果总和的高位。

49. 发明授权

US08604832B1 Time division multiplexed limited switch dynamic logic 失效
公开(公告)号：US08604832B1
公开(公告)日：2013-12-10
申请号：US13524562
申请日：2012-06-15
申请人： Leland Chang , Robert K. Montoye , Yutaka Nakamura
发明人： Leland Chang , Robert K. Montoye , Yutaka Nakamura
IPC分类号： H03K19/00
CPC分类号： H03K19/0963 , H03K19/096
摘要： A method for increasing performance in a limited switch dynamic logic (LSDL) circuit includes precharging a dynamic node during a precharge phase of a first and second evaluation clock signal. The dynamic node is evaluated to a first logic value in response to one or more first input signals of a first evaluation tree during an evaluation phase of the first evaluation clock signal. The dynamic node is evaluated to a second logic value in response one or more second input signals of a second evaluation tree during an evaluation phase of the second evaluation clock signal. A signal of the LSDL circuit is outputted in response to the dynamic node according to an output latch clock signal.

50. 发明申请

US20130151818A1 MICRO ARCHITECTURE FOR INDIRECT ACCESS TO A REGISTER FILE IN A PROCESSOR 审中-公开
标题翻译：用于间接访问处理器中的寄存器文件的微结构
公开(公告)号：US20130151818A1
公开(公告)日：2013-06-13
申请号：US13323933
申请日：2011-12-13
申请人： Erez Barak , Alejandro Rico Carro , Jeffrey H. Derby , Amit Golander , Omer Heymann , Nadav Levison , Sagi Manole , Robert K. Montoye
发明人： Erez Barak , Alejandro Rico Carro , Jeffrey H. Derby , Amit Golander , Omer Heymann , Nadav Levison , Sagi Manole , Robert K. Montoye
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3838 , G06F9/3013 , G06F9/30138 , G06F9/35 , G06F9/3826
摘要： A method and system for improving performance and latency of instruction execution within an execution pipeline in a processor. The method includes finding, while decoding an instruction, a pointer register used by the instruction; reading the pointer register; validating a pointer register entry; reading, if the pointer register entry is valid, a register file entry; validating a register file entry; validating, if the register file entry is invalid, a valid register file entry wherein the valid register file entry is in the register file's future file; bypassing, if the valid register file entry is valid, a valid register file value from the register file's future file to the execution pipeline wherein the valid register file value is in the valid register file entry; and executing the instruction using the valid register file value; wherein at least one of the steps is carried out using a computer device.
摘要翻译：一种用于改善处理器中的执行流水线内的指令执行的性能和延迟的方法和系统。该方法包括在解码指令时发现指令使用的指针寄存器; 读指针寄存器; 验证指针寄存器条目; 如果指针寄存器条目有效，读取寄存器文件条目; 验证注册文件条目; 如果注册文件条目无效，验证有效的注册文件条目，其中有效的注册文件条目在注册文件的未来文件中; 绕过，如果有效的注册文件条目有效，则从注册文件的未来文件到执行管道的有效注册文件值，其中有效的注册文件值在有效的注册文件条目中; 并使用有效的寄存器文件值执行指令; 其中使用计算机设备执行所述步骤中的至少一个。

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