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41. 发明授权

US07575975B2 Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer 有权
标题翻译：用于形成具有应变半导体层的平面和垂直半导体结构的方法
公开(公告)号：US07575975B2
公开(公告)日：2009-08-18
申请号：US11263120
申请日：2005-10-31
申请人： Voon-Yew Thean , Jian Chen , Bich-Yen Nguyen , Mariam G. Sadaka , Da Zhang
发明人： Voon-Yew Thean , Jian Chen , Bich-Yen Nguyen , Mariam G. Sadaka , Da Zhang
IPC分类号： H01L21/00 , H01L21/84 , H01L21/8234 , H01L27/088
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/7842 , H01L29/785 , Y10S438/938
摘要： Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.
摘要翻译：形成半导体结构包括提供具有覆盖在绝缘层上的应变半导体层的衬底，提供用于形成具有第一导电类型的第一多个器件的第一器件区域，提供第二器件区域，用于形成具有第第二导电类型，并且使第二器件区域中的应变半导体层变厚，使得第二器件区域中的应变半导体层具有较小的第一器件区域中的应变半导体层的应变。或者，形成半导体结构包括提供具有第一导电类型的第一区域，形成覆盖第一区域的至少有源区域的绝缘层，各向异性地蚀刻绝缘层，以及在各向异性蚀刻绝缘层之后，覆盖绝缘层的至少一部分的材料。

42. 发明授权

US07205210B2 Semiconductor structure having strained semiconductor and method therefor 有权
标题翻译：具有应变半导体的半导体结构及其方法
公开(公告)号：US07205210B2
公开(公告)日：2007-04-17
申请号：US10780143
申请日：2004-02-17
申请人： Alexander L. Barr , Dejan Jovanovic , Bich-Yen Nguyen , Mariam G. Sadaka , Voon-Yew Thean , Ted R. White
发明人： Alexander L. Barr , Dejan Jovanovic , Bich-Yen Nguyen , Mariam G. Sadaka , Voon-Yew Thean , Ted R. White
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L27/1203 , H01L21/76254 , H01L21/823412 , H01L21/823807 , H01L21/84
摘要： A first semiconductor structure has a silicon substrate, a first silicon germanium layer grown on the silicon, a second silicon germanium layer on the first silicon germanium layer, and a strained silicon layer on the second silicon germanium layer. A second semiconductor structure has a silicon substrate and an insulating top layer. The silicon layer of the first semiconductor structure is bonded to the insulator layer to form a third semiconductor structure. The second silicon germanium layer is cut to separate most of the first semiconductor structure from the third semiconductor structure. The silicon germanium layer is removed to expose the strained silicon layer where transistors are subsequently formed, which is then the only layer remaining from the first semiconductor structure. The transistors are oriented along the direction and at a 45 degree angle to the direction of the base silicon layer of the second silicon.
摘要翻译：第一半导体结构具有硅衬底，在硅上生长的第一硅锗层，第一硅锗层上的第二硅锗层和第二硅锗层上的应变硅层。第二半导体结构具有硅衬底和绝缘顶层。第一半导体结构的硅层被结合到绝缘体层以形成第三半导体结构。切割第二硅锗层以将大部分第一半导体结构与第三半导体结构分离。去除硅锗层以暴露随后形成晶体管的应变硅层，其后是从第一半导体结构残留的唯一层。晶体管沿着<100>方向定向并且与第二硅的基底硅层的<100>方向成45度角。

43. 发明申请

US20060076579A1 Semiconductor transistor having structural elements of differing materials 有权
标题翻译：具有不同材料结构元件的半导体晶体管
公开(公告)号：US20060076579A1
公开(公告)日：2006-04-13
申请号：US11247866
申请日：2005-10-07
申请人： Voon-Yew Thean , Dina Triyoso , Bich-Yen Nguyen
发明人： Voon-Yew Thean , Dina Triyoso , Bich-Yen Nguyen
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L21/823878 , H01L21/84 , H01L29/165 , H01L29/517 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7848
摘要： A transistor is formed using a semiconductor substrate and forming a control electrode overlying the semiconductor substrate. A first current electrode is formed within the semiconductor substrate and adjacent the control electrode. The first current electrode has a first predetermined semiconductor material. A second current electrode is formed within the semiconductor substrate and adjacent the control electrode to form a channel within the semiconductor substrate. The second current electrode has a second predetermined semiconductor material that is different from the first predetermined semiconductor material. The first predetermined semiconductor material is chosen to optimize bandgap energy of the first current electrode, and the second predetermined semiconductor material is chosen to optimize strain of the channel.
摘要翻译：使用半导体衬底形成晶体管，并形成覆盖半导体衬底的控制电极。第一电流电极形成在半导体衬底内并与控制电极相邻。第一电流电极具有第一预定半导体材料。第二电流电极形成在半导体衬底内并与控制电极相邻，以在半导体衬底内形成通道。第二电流电极具有与第一预定半导体材料不同的第二预定半导体材料。选择第一预定半导体材料以优化第一电流电极的带隙能量，并且选择第二预定半导体材料以优化通道的应变。

44. 发明授权

US08039341B2 Selective uniaxial stress modification for use with strained silicon on insulator integrated circuit 有权
标题翻译：用于应变硅绝缘体集成电路的选择性单轴应力修正
公开(公告)号：US08039341B2
公开(公告)日：2011-10-18
申请号：US11428953
申请日：2006-07-06
申请人： Voon-Yew Thean , Bich-Yen Nguyen , Da Zhang
发明人： Voon-Yew Thean , Bich-Yen Nguyen , Da Zhang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor fabrication process includes masking a first region, e.g., an NMOS region, of a semiconductor wafer, e.g., a biaxial, tensile strained silicon on insulator (SOI) wafer and creating recesses in source/drain regions of a second wafer region, e.g., a PMOS region. The wafer is then annealed in an ambient that promotes migration of silicon. The source/drain recesses are filled with source/drain structures, e.g., by epitaxial growth. The anneal ambient may include a hydrogen bearing species, e.g., H2 or GeH2, maintained at a temperature in the range of approximately 800 to 1000° C. The second region may be silicon and the source/drain structures may be silicon germanium. Creating the recesses may include creating shallow recesses with a first etch process, performing an amorphizing implant to create an amorphous layer, performing an inert ambient anneal to recrystallize the amorphous layer, and deepening the shallow recesses with a second etch process.
摘要翻译：半导体制造工艺包括掩蔽半导体晶片的第一区域（例如，NMOS区域），例如双轴拉伸应变绝缘体上硅（SOI）晶片，并在第二晶片区域的源极/漏极区域中产生凹陷，例如，PMOS区域。然后将晶片在促进硅迁移的环境中退火。源极/漏极凹槽用源极/漏极结构填充，例如通过外延生长。退火环境可以包括保持在约800至1000℃范围内的温度的氢气种类，例如H 2或GeH 2。第二区域可以是硅，并且源极/漏极结构可以是硅锗。创建凹槽可以包括用第一蚀刻工艺创建浅凹槽，执行非晶化注入以产生非晶层，执行惰性环境退火以使非晶层重结晶，以及用第二蚀刻工艺加深浅凹槽。

45. 发明授权

US07781840B2 Semiconductor device structure 有权
标题翻译：半导体器件结构
公开(公告)号：US07781840B2
公开(公告)日：2010-08-24
申请号：US11742955
申请日：2007-05-01
申请人： Ted R. White , Alexander L. Barr , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean
发明人： Ted R. White , Alexander L. Barr , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/66772
摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
摘要翻译：在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。然后在氧掺杂半导体层上外延生长半导体层。在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。不同类型的晶体管形成在不同的结晶取向上。

46. 发明授权

US07615806B2 Method for forming a semiconductor structure and structure thereof 有权
标题翻译：半导体结构的形成方法及其结构
公开(公告)号：US07615806B2
公开(公告)日：2009-11-10
申请号：US11263119
申请日：2005-10-31
申请人： Voon-Yew Thean , Jian Chen , Bich-Yen Nguyen , Mariam G. Sadaka , Da Zhang
发明人： Voon-Yew Thean , Jian Chen , Bich-Yen Nguyen , Mariam G. Sadaka , Da Zhang
IPC分类号： H01L27/10
CPC分类号： H01L21/823807 , H01L21/823821 , H01L21/82385 , H01L21/845 , H01L27/1211 , H01L29/7842 , H01L29/785
摘要： Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.
摘要翻译：形成半导体结构包括提供具有覆盖在绝缘层上的应变半导体层的衬底，提供用于形成具有第一导电类型的第一多个器件的第一器件区域，提供第二器件区域，用于形成具有第第二导电类型，并且使第二器件区域中的应变半导体层变厚，使得第二器件区域中的应变半导体层具有较小的第一器件区域中的应变半导体层的应变。或者，形成半导体结构包括提供具有第一导电类型的第一区域，形成覆盖第一区域的至少有源区域的绝缘层，各向异性地蚀刻绝缘层，以及在各向异性蚀刻绝缘层之后，覆盖绝缘层的至少一部分的材料。

47. 发明申请

US20070277728A1 METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE HAVING A STRAINED SILICON LAYER 有权
标题翻译：用于形成具有应变硅层的半导体结构的方法
公开(公告)号：US20070277728A1
公开(公告)日：2007-12-06
申请号：US11421009
申请日：2006-05-30
申请人： Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Ted R. White
发明人： Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Ted R. White
IPC分类号： C30B21/04 , C30B13/00
CPC分类号： C30B29/52 , C30B25/02 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L21/76254
摘要： A wafer having a silicon layer that is strained is used to form transistors. The silicon layer is formed by first forming a silicon germanium (SiGe) layer of at least 30 percent germanium that has relaxed strain on a donor wafer. A thin silicon layer is epitaxially grown to have tensile strain on the relaxed SiGe layer. The amount tensile strain is related to the germanium concentration. A high temperature oxide (HTO) layer is formed on the thin silicon layer by reacting dichlorosilane and nitrous oxide at a temperature of preferably between 800 and 850 degrees Celsius. A handle wafer is provided with a supporting substrate and an oxide layer that is then bonded to the HTO layer. The HTO layer, being high density, is able to hold the tensile strain of the thin silicon layer. The relaxed SiGe layer is cleaved then etched away to expose the thin silicon layer. A low temperature silicon layer is then epitaxially grown with tensile strain, correlated to the tensile strain of the thin silicon layer, on the thin silicon layer using trisilane at a temperature preferably not in excess of 500 degrees Celsius. The resulting tensile strain, correlated to the strain of the thin silicon layer, is thus also correlated to the germanium concentration of the relaxed SiGe layer. The thickness of the low temperature silicon layer, using the trisilane at low temperature, is significantly greater than what would normally be expected for a silicon layer of that tensile strain.
摘要翻译：具有应变的硅层的晶片用于形成晶体管。通过首先在施主晶片上形成具有松弛应变的至少30％的锗的锗锗（SiGe）层来形成硅层。外延生长薄硅层以在松弛的SiGe层上具有拉伸应变。拉伸应变量与锗浓度有关。优选在800至850摄氏度之间的温度下，通过使二氯硅烷和一氧化二氮反应，在薄硅层上形成高温氧化物（HTO）层。手柄晶片设置有支撑基板和氧化物层，然后将其结合到HTO层。高密度的HTO层能够保持薄硅层的拉伸应变。松弛的SiGe层被切割，然后蚀刻掉以露出薄的硅层。然后在优选不超过500摄氏度的温度下使用丙硅烷在薄硅层上外延生长与低硅薄层的拉伸应变相关的低温硅层。因此，与薄硅层的应变相关的所得拉伸应变也与弛豫SiGe层的锗浓度相关。在低温下使用丙硅烷的低温硅层的厚度明显大于该拉伸应变的硅层通常预期的厚度。

48. 发明授权

US07282402B2 Method of making a dual strained channel semiconductor device 有权
标题翻译：制造双应变通道半导体器件的方法
公开(公告)号：US07282402B2
公开(公告)日：2007-10-16
申请号：US11093801
申请日：2005-03-30
申请人： Mariam G. Sadaka , Alexander L. Barr , Dejan Jovanovic , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
发明人： Mariam G. Sadaka , Alexander L. Barr , Dejan Jovanovic , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.
摘要翻译：根据本公开的实施例，制造双应变通道半导体器件的过程包括将应变Si和压缩SiGe与沟槽隔离相集成，以实现同时的NMOS和PMOS性能增强。如本文所述，NMOS和PMOS的集成可以以几种方式实现，以实现与浅沟槽隔离兼容的NMOS和PMOS沟道。

49. 发明授权

US07160769B2 Channel orientation to enhance transistor performance 有权
标题翻译：通道方向增强晶体管性能
公开(公告)号：US07160769B2
公开(公告)日：2007-01-09
申请号：US10969108
申请日：2004-10-20
申请人： Ted R. White , Alexander L. Barr , Dejan Jovanovic , Bich-Yen Nguyen , Mariam G. Sadaka , Voon-Yew Thean
发明人： Ted R. White , Alexander L. Barr , Dejan Jovanovic , Bich-Yen Nguyen , Mariam G. Sadaka , Voon-Yew Thean
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/78 , H01L21/823807 , H01L27/092 , H01L29/045
摘要： P channel transistors are formed in a semiconductor layer that has a (110) surface orientation for enhancing P channel transistor performance, and the N channel transistors are formed in a semiconductor layer that has a (100) surface orientation. To further provide P channel transistor performance enhancement, the direction of their channel lengths is selected based on their channel direction. The narrow width P channel transistors are preferably oriented in the direction. The wide channel width P channel transistors are preferably oriented in the direction.
摘要翻译： P沟道晶体管形成在具有用于增强P沟道晶体管性能的（110）表面取向的半导体层中，并且N沟道晶体管形成在具有（100）表面取向的半导体层中。为了进一步提供P沟道晶体管性能增强，它们的沟道长度的方向根据其沟道方向来选择。窄宽度P沟道晶体管优选地在<100>方向上取向。宽通道宽度P沟道晶体管优选地在<110>方向上取向。

50. 发明授权

US07091071B2 Semiconductor fabrication process including recessed source/drain regions in an SOI wafer 有权
标题翻译：半导体制造工艺包括在SOI晶片中的凹陷源极/漏极区域
公开(公告)号：US07091071B2
公开(公告)日：2006-08-15
申请号：US11028811
申请日：2005-01-03
申请人： Voon-Yew Thean , Brian J. Goolsby , Bich-Yen Nguyen , Thien T. Nguyen , Tab A. Stephens
发明人： Voon-Yew Thean , Brian J. Goolsby , Bich-Yen Nguyen , Thien T. Nguyen , Tab A. Stephens
IPC分类号： H01L21/00
CPC分类号： H01L29/66636 , H01L29/66772 , H01L29/78639
摘要： A method of forming a transistor with recessed source/drains in an silicon-on-insulator (SOI) wafer includes forming isolation structures in an active layer of the wafer, where the isolation structures preferably extend through the active layer to a BOX layer of the wafer. An upper portion of the active layer is removed to form a transistor channel structure. A gate dielectric is formed on the channel structure and a gate structure is formed on the gate dielectric. Etching through exposed portions of the gate dielectric, channel structure, and BOX layer is performed and source/drain structures are then grown epitaxially from exposed portions of the substrate bulk. The isolation structure and the BOX layer are both comprised primarily of silicon oxide and the thickness of the isolation structure prevents portions of the BOX layer from being etched.
摘要翻译：在绝缘体上硅（SOI）晶片中形成具有凹陷源/漏极的晶体管的方法包括在晶片的有源层中形成隔离结构，其中隔离结构优选地延伸穿过有源层到BOX层的BOX层晶圆。去除有源层的上部以形成晶体管沟道结构。在沟道结构上形成栅极电介质，在栅极电介质上形成栅极结构。执行蚀刻通过栅介质，沟道结构和BOX层的暴露部分，然后从衬底体的暴露部分外延生长源极/漏极结构。隔离结构和BOX层主要由氧化硅组成，并且隔离结构的厚度防止BOX层的部分被蚀刻。

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