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41. 发明授权

US4822753A Method for making a w/tin contact 失效
标题翻译：制造w /锡接触的方法
公开(公告)号：US4822753A
公开(公告)日：1989-04-18
申请号：US191637
申请日：1988-05-09
申请人： Faivel Pintchovski , Philip J. Tobin
发明人： Faivel Pintchovski , Philip J. Tobin
IPC分类号： H01L21/768 , H01L21/283 , H01L21/316
CPC分类号： H01L21/76879 , Y10S148/02 , Y10S148/051 , Y10S148/106 , Y10S438/926
摘要： A method is disclosed for fabricating a semiconductor device and especially for contacting a semiconductor device. A silicon substrate is provided which has a device region formed at the surface thereof and which is contacted with a silicide. An insulating layer overlies the substrate and has an opening therethrough which exposes a portion of that device region. Titanium nitride is deposited in a blanket layer overlying the silicide and the insulating layer. A leveling agent such as a spin-on glass is applied to the structure to substantially fill the opening. That leveling agent is then anisotropically etched to leave the leveling agent only in the opening. The leveling agent is used as an etch mask to remove the portion of titanium nitride which is located outside the opening. After removing the remaining leveling agent, the titanium nitride in the opening is used as a nucleating surface for the selective deposition of a tungsten plug which fills the contact opening. The titanium nitride layer serves as both a nucleating surface and as a barrier layer which separates the tungsten from the underlying silicon.
摘要翻译：公开了用于制造半导体器件的方法，特别是用于接触半导体器件。提供硅衬底，其具有在其表面形成并与硅化物接触的器件区域。绝缘层覆盖在衬底上并具有通过其穿过的开口，露出该器件区域的一部分。氮化钛沉积在覆盖硅化物和绝缘层的覆盖层中。将均化剂如旋涂玻璃施加到结构上以基本上填充开口。然后对流平剂进行各向异性蚀刻，仅在开口处离开流平剂。流平剂用作蚀刻掩模以去除位于开口外部的氮化钛部分。在除去剩余的流平剂之后，将开口中的氮化钛用作用于选择性沉积填充接触开口的钨丝塞的成核表面。氮化钛层既用作成核的表面又用作将钨与下面的硅分离开的阻挡层。

42. 发明授权

US4819040A Epitaxial CMOS by oxygen implantation 失效
标题翻译：外延CMOS通过氧气注入
公开(公告)号：US4819040A
公开(公告)日：1989-04-04
申请号：US243208
申请日：1988-09-09
申请人： Philip J. Tobin
发明人： Philip J. Tobin
IPC分类号： H01L27/092 , H01L27/02 , H01L27/04 , H01L29/167
CPC分类号： H01L27/0928
摘要： A technique for selectively implanting regions of semiconductor crystals with oxygen to increase their yield strength. This intentional, selective oxygen pinning technique is especially useful in causing underlying, originally oxygen-free silicon to be more resistant to plastic deformation during isolation field oxide formation processes. Oxide regions grown on a substrate cause stress at the oxide/substrate interface and typically dislocation and other stress induced crystallographic defects at and near the point of stress, especially if the substrate is essentially oxygen-free. Dislocation and other crystallographic defects that occur in the areas of device formation and p/n junctions can cause junction leakage and active device degradation.
摘要翻译：用氧选择性地注入半导体晶体区域以提高其屈服强度的技术。这种有意的选择性氧气钉扎技术特别适用于在隔离场氧化物形成过程中使底层的原始无氧硅更能抵抗塑性变形。在衬底上生长的氧化物区域在氧化物/衬底界面处引起应力，并且在应力点处和附近通常会发生位错和其他应力引起的晶体缺陷，特别是如果衬底基本上是无氧的。在器件形成和p / n结区域中发生的位错和其他晶体缺陷可能导致结漏电和器件劣化。

43. 发明授权

US4605947A Titanium nitride MOS device gate electrode and method of producing 失效
标题翻译：氮化钛MOS器件栅电极及其制造方法
公开(公告)号：US4605947A
公开(公告)日：1986-08-12
申请号：US779533
申请日：1985-09-24
申请人： J. B. Price , Philip J. Tobin , Fabio Pintchovski , Christian A. Seelbach
发明人： J. B. Price , Philip J. Tobin , Fabio Pintchovski , Christian A. Seelbach
IPC分类号： H01L21/318 , H01L21/3205 , H01L23/532 , H01L29/49 , H01L29/78 , H01L23/50 , H01L23/52 , H01L29/62
CPC分类号： H01L23/53257 , H01L21/318 , H01L21/32051 , H01L29/4925 , H01L29/4966 , H01L2924/0002
摘要： An MOS device having a gate electrode and interconnect of titanium nitride and especially titanium nitride which is formed by low pressure chemical vapor deposition. In a more specific embodiment the titanium nitride gate electrode and interconnect have a silicon layer thereover to improve oxidation protection.
摘要翻译：具有栅极的MOS器件和通过低压化学气相沉积形成的氮化钛特别是氮化钛的互连。在更具体的实施例中，氮化钛栅电极和互连件具有其上的硅层以改善氧化保护。

44. 发明授权

US08178401B2 Method for fabricating dual-metal gate device 有权
标题翻译：双金属栅极器件制造方法
公开(公告)号：US08178401B2
公开(公告)日：2012-05-15
申请号：US11530058
申请日：2006-09-08
申请人： David C. Gilmer , Srikanth B. Samavedam , Philip J. Tobin
发明人： David C. Gilmer , Srikanth B. Samavedam , Philip J. Tobin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.
摘要翻译：一种制造包括由异型金属形成的双金属栅极的MOS晶体管的方法。诸如HfO 2的栅极电介质（34）沉积在半导体衬底上。牺牲层（35）接着沉积在栅极电介质上。牺牲层被图案化，使得衬底的第一（pMOS，例如）区域（32）上的栅极电介质被暴露，并且衬底的第二（nMOS，例如）区域（33）上的栅极电介质继续是受牺牲层保护。第一栅极导体材料（51）沉积在剩余的牺牲区域上并暴露在栅极电介质上。图案化第一栅极导体材料，使得衬底的第二区域上方的第一栅极导体材料被蚀刻掉。第二区域上的牺牲层防止在去除第一栅极导体材料时损坏下面的介电材料。

45. 发明授权

US06717226B2 Transistor with layered high-K gate dielectric and method therefor 有权
标题翻译：具有层状高K栅极电介质的晶体管及其方法
公开(公告)号：US06717226B2
公开(公告)日：2004-04-06
申请号：US10098706
申请日：2002-03-15
申请人： Rama I. Hegde , Joe Mogab , Philip J. Tobin , Hsing H. Tseng , Chun-Li Liu , Leonard J. Borucki , Tushar P. Merchant , Christopher C. Hobbs , David C. Gilmer
发明人： Rama I. Hegde , Joe Mogab , Philip J. Tobin , Hsing H. Tseng , Chun-Li Liu , Leonard J. Borucki , Tushar P. Merchant , Christopher C. Hobbs , David C. Gilmer
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A transistor device has a gate dielectric with at least two layers in which one is hafnium oxide and the other is a metal oxide different from hafnium oxide. Both the hafnium oxide and the metal oxide also have a high dielectric constant. The metal oxide provides an interface with the hafnium oxide that operates as a barrier for contaminant penetration. Of particular concern is boron penetration from a polysilicon gate through hafnium oxide to a semiconductor substrate. The hafnium oxide will often have grain boundaries in its crystalline structure that provide a path for boron atoms. The metal oxide has a different structure than that of the hafnium oxide so that those paths for boron in the hafnium oxide are blocked by the metal oxide. Thus, a high dielectric constant is provided while preventing boron penetration from the gate electrode to the substrate.
摘要翻译：晶体管器件具有至少两层的栅极电介质，其中一个是氧化铪，另一个是不同于氧化铪的金属氧化物。氧化铪和金属氧化物也具有高介电常数。金属氧化物提供与氧化铪的界面，其作为污染物渗透的屏障。特别值得注意的是硼从多晶硅栅极渗透到氧化铪到半导体衬底。氧化铪在其结晶结构中通常具有晶界，其提供硼原子的路径。金属氧化物具有与氧化铪不同的结构，使得氧化铪中的硼的路径被金属氧化物阻挡。因此，提供高介电常数，同时防止硼从栅电极渗透到基板。

46. 发明授权

US06432779B1 Selective removal of a metal oxide dielectric 有权
标题翻译：选择性去除金属氧化物电介质
公开(公告)号：US06432779B1
公开(公告)日：2002-08-13
申请号：US09772632
申请日：2001-01-30
申请人： Christopher Hobbs , Rama I. Hegde , Philip J. Tobin
发明人： Christopher Hobbs , Rama I. Hegde , Philip J. Tobin
IPC分类号： H01L21336
CPC分类号： H01L21/28035 , H01L21/2807 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/3105 , H01L21/31111 , H01L21/31116 , H01L21/31122 , H01L21/32136 , H01L29/4966 , H01L29/517 , H01L29/518
摘要： A method for forming a semiconductor device is disclosed in which a metal oxide gate dielectric layer is formed over a substrate. A gate electrode is then formed over the metal oxide layer thereby exposing a portion of the metal oxide layer. The exposed portion of the metal oxide gate dielectric layer is then chemically reduced to a metal or a metal hydride. The metal or metal hydride is then removed with a conventional wet etch or wet/dry etch combination. The metal oxide layer may include a metal element such as zirconium, tantalum, hafnium, titanium, or lanthanum and may further include an additional element such as silicon or nitrogen. Reducing the metal oxide layer may includes annealing the metal oxide gate dielectric layer in an ambient with an oxygen partial pressure that is less than a critical limit for oxygen desorption at a given temperature. In another embodiment, reducing the metal oxide gate dielectric layer may include annealing the metal oxide layer while supplying a hydrogen-containing precursor such as silane, ammonia, germane, hydrogen, and hydrazine to the metal oxide gate dielectric layer. The gate electrode may comprise a gate electrode stack that includes a titanium nitride layer over the metal oxide gate dielectric layer and a silicon-containing capping layer over the titanium nitride layer.
摘要翻译：公开了一种用于形成半导体器件的方法，其中在衬底上形成金属氧化物栅极电介质层。然后在金属氧化物层上形成栅电极，从而暴露金属氧化物层的一部分。然后将金属氧化物栅介质层的暴露部分化学还原成金属或金属氢化物。然后用常规的湿蚀刻或湿/干蚀刻组合去除金属或金属氢化物。金属氧化物层可以包括诸如锆，钽，铪，钛或镧的金属元素，并且还可以包括另外的元素如硅或氮。还原金属氧化物层可以包括在氧气分压下在金属氧化物栅极电介质层中退火，其氧分压小于在给定温度下氧解吸的临界极限。在另一个实施方案中，还原金属氧化物栅极电介质层可以包括使金属氧化物层退火，同时向金属氧化物栅极电介质层供应诸如硅烷，氨，锗烷，氢和肼的含氢前体。栅电极可以包括栅极电极堆叠，其在金属氧化物栅极介电层上方包括氮化钛层，并且在氮化钛层上方包含含硅覆盖层。

47. 发明授权

US06383873B1 Process for forming a structure 有权
标题翻译：形成结构的方法
公开(公告)号：US06383873B1
公开(公告)日：2002-05-07
申请号：US09575204
申请日：2000-05-18
申请人： Rama I. Hegde , Philip J. Tobin , Amit Nangia
发明人： Rama I. Hegde , Philip J. Tobin , Amit Nangia
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/28194 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A finished structure (100) includes a semiconductive region (102), a first oxide layer (106), a second oxide layer (108), and a conductive layer (110). The first oxide layer (106) lies between the semiconductive region (102) and the second oxide layer (108); and the second oxide layer (108) lies between the first oxide layer (106) and the conductive layer (110). The first oxide layer (106) includes at least a portion that is amorphous or includes a first element, a second element, and a third element. In the latter, the first element is a metallic element, and each of the first, second, and third elements are different from each other. A process for forming a structure (100) includes forming a first layer (106) near a semiconductive region (102), forming a second layer (108) after forming the first layer (106), and forming a third layer (110) after forming the second layer (108). The first oxide layer (106) includes a metallic element and oxygen. The third layer (110) is a non-insulating layer.
摘要翻译：完成的结构（100）包括半导体区域（102），第一氧化物层（106），第二氧化物层（108）和导电层（110）。第一氧化物层（106）位于半导电区域（102）和第二氧化物层（108）之间; 并且所述第二氧化物层（108）位于所述第一氧化物层（106）和所述导电层（110）之间。第一氧化物层（106）包括至少一部分，其是无定形的或包括第一元件，第二元件和第三元件。在后者中，第一元件是金属元件，并且第一元件，第二元件和第三元件中的每一个元件彼此不同。用于形成结构（100）的方法包括在半导体区域（102）附近形成第一层（106），在形成第一层（106）之后形成第二层（108），以及在形成第三层之后形成第三层（110）形成第二层（108）。第一氧化物层（106）包括金属元素和氧。第三层（110）是非绝缘层。

48. 发明授权

US06063698A Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits 失效
标题翻译：制造用于半导体集成电路的高介电常数栅极氧化物的方法
公开(公告)号：US06063698A
公开(公告)日：2000-05-16
申请号：US885433
申请日：1997-06-30
申请人： Hsing-Huang Tseng , Philip J. Tobin
发明人： Hsing-Huang Tseng , Philip J. Tobin
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/51 , H01L21/3205
CPC分类号： H01L29/6659 , H01L21/28176 , H01L21/28247 , H01L29/4983 , H01L21/28194 , H01L21/28202 , H01L29/517 , H01L29/518 , H01L29/6656 , Y10S438/91
摘要： A method for forming a gate dielectric (14b) begins by providing a substrate (12). A high K dielectric layer (14a) is deposited overlying the substrate (12). The dielectric layer (14a) contains bulk traps (16) and interface traps (18). A polysilicon gate electrode (20) is then patterned and etched overlying the gate dielectric (14a) whereby the plasma etching of the gate electrode (20) results in substrate plasma damage (22). A post gate wet oxidation process is performed between 750.degree. C. and 850.degree. C. to reduce plasma etch damage and trap sites (16, 18) in order to provide an improved gate dielectric (14b). Source and drain electrodes (30) are then formed within the substrate and laterally adjacent the gate electrode (20) to form a transistor device having more consistent threshold voltages, improved subthreshold slope operation, reduced gate to channel leakage, and improved speed of operation.
摘要翻译：形成栅极电介质（14b）的方法开始于提供衬底（12）。沉积在基底（12）上的高K电介质层（14a）。电介质层（14a）包含大量阱（16）和界面阱（18）。然后将多晶硅栅电极（20）图案化并蚀刻在栅极电介质（14a）上，由此栅电极（20）的等离子体蚀刻导致衬底等离子体损伤（22）。在750℃至850℃之间进行后门湿氧化处理以减少等离子体蚀刻损伤和捕集位点（16,18），以提供改进的栅极电介质（14b）。源极和漏极（30）然后形成在衬底内并且横向邻近栅电极（20），以形成具有更一致的阈值电压，改进的亚阈值斜率操作，减小的栅极到沟道泄漏以及改善的操作速度的晶体管器件。

49. 发明授权

US5726087A Method of formation of semiconductor gate dielectric 失效
标题翻译：形成半导体栅极电介质的方法
公开(公告)号：US5726087A
公开(公告)日：1998-03-10
申请号：US258360
申请日：1994-06-09
申请人： Hsing-Huang Tseng , Philip J. Tobin
发明人： Hsing-Huang Tseng , Philip J. Tobin
IPC分类号： H01L21/28 , H01L21/336 , H01L29/08 , H01L29/51 , H01L21/318
CPC分类号： H01L21/28185 , H01L21/28035 , H01L21/28176 , H01L21/28238 , H01L21/28273 , H01L29/0847 , H01L29/513 , H01L29/518 , H01L29/66575 , H01L21/28194 , H01L21/28211
摘要： A semiconductor dielectric (10) is formed by providing a base layer (12) having a surface. A thin interface layer (13) is formed at the surface of the base layer (12). The thin interface layer has a substantial concentration of one of either nitrogen or fluorine. A thermal oxide layer (14) is formed overlying the interface layer (13). A deposited dielectric layer (16) is formed overlying the thermal oxide layer (14). The deposited dielectric layer (16) is optionally densified by a thermal heat cycle. The deposited dielectric layer (16) has micropores that are misaligned to micropores in the thermal oxide layer (14) to provide enhanced features.
摘要翻译：通过提供具有表面的基底层（12）形成半导体电介质（10）。在基层（12）的表面形成有薄界面层（13）。薄界面层具有大量浓度的氮或氟之一。在界面层（13）上形成热氧化层（14）。沉积的介电层（16）形成在热氧化物层（14）上。沉积的介电层（16）任选地通过热热循环致密化。沉积的介电层（16）具有与热氧化物层（14）中的微孔不对准的微孔，以提供增强的特征。

50. 发明授权

US5571734A Method for forming a fluorinated nitrogen containing dielectric 失效
标题翻译：形成含氟含氮电介质的方法
公开(公告)号：US5571734A
公开(公告)日：1996-11-05
申请号：US316175
申请日：1994-10-03
申请人： Hsing-Huang Tseng , Philip J. Tobin
发明人： Hsing-Huang Tseng , Philip J. Tobin
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/318 , H01L21/324 , H01L21/336 , H01L29/51 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/225 , H01L21/3115
CPC分类号： H01L21/28185 , H01L21/28176 , H01L21/28202 , H01L29/513 , H01L29/518 , H01L21/28211
摘要： This disclosure reveals a manufacturable and controllable method to fabricate a dielectric which increases the device current drive. A nitrogen-containing ambient is used to oxidize a surface of a substrate (10) to form a nitrogen-containing dielectric (12). Then a fluorine-containing specie (F) is introduced, preferably through implanting, into a gate electrode (20) overlying the nitrogen-containing dielectric. The fluorine is then driven into the underlying nitrogen-containing dielectric. A fluorinated nitrogen-containing region (14') is expected to form at the interface between dielectric (12') and substrate (10). The interaction between fluorine and nitrogen increases the peak transconductance as well as the transconductance at a high electric field for the dielectric. Therefore, the overall current drive is increased by this approach.
摘要翻译：本公开揭示了可制造和可控制的方法来制造增加器件电流驱动的电介质。使用含氮环境来氧化衬底（10）的表面以形成含氮电介质（12）。然后，优选通过注入将含氟物质（F）引入覆盖含氮电介质的栅电极（20）中。然后将氟驱动到下面的含氮电介质中。期望在电介质（12'）和衬底（10）之间的界面处形成含氟含氮区域（14'）。氟和氮之间的相互作用增加了在电介质的高电场下的峰跨越以及跨导。因此，通过这种方法增加了整体目前的驱动力。

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