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41. 发明申请

US20050186986A1 WLAN transmitter having high data throughput 有权
标题翻译： WLAN发射机具有高数据吞吐量
公开(公告)号：US20050186986A1
公开(公告)日：2005-08-25
申请号：US10856023
申请日：2004-05-28
申请人： Christopher Hansen , Jason Trachewsky , Nambirajan Seshadri , Kelly Cameron , Hau Tran , Ba-Zhong Shen
发明人： Christopher Hansen , Jason Trachewsky , Nambirajan Seshadri , Kelly Cameron , Hau Tran , Ba-Zhong Shen
IPC分类号： H03C7/02 , H04B1/02 , H04B1/66 , H04B7/02 , H04L1/00 , H04L1/06 , H04L25/03
CPC分类号： H04W4/18 , H04L1/0057 , H04L1/0059 , H04L1/0065 , H04L1/0066 , H04L1/0068 , H04L1/0071 , H04L1/0618 , H04L25/03866 , H04L27/2601 , H04W84/12 , H04W88/10
摘要： A wireless local area network (WLAN) transmitter includes a baseband processing module and a plurality of radio frequency (RF) transmitters. The baseband processing module is operably coupled to process data by scrambling the data in accordance with a pseudo random sequence to produce scrambled data. The processing of the data continues by selecting one of a plurality of encoding modes based on a mode selection signal. The processing of the data continues by encoding the scrambled data in accordance with the one of the plurality of encoding modes to produce encoded data. The processing of the data continues by determining a number of transmit streams based on the mode selection signal. The processing of the data further continues by converting the encoded data into streams of symbols in accordance with the number of transmit streams and the mode selection signal. A number of the plurality of RF transmitters are enabled based on the mode selection signal to convert a corresponding one of the streams of symbols into a corresponding RF signal such that a corresponding number of RF signals is produced.
摘要翻译：无线局域网（WLAN）发射机包括基带处理模块和多个射频（RF）发射机。基带处理模块可操作地耦合以通过根据伪随机序列对数据进行加扰来处理数据以产生加扰数据。基于模式选择信号，选择多种编码模式之一来继续数据的处理。通过根据多个编码模式之一对加扰数据进行编码，继续处理数据以产生编码数据。通过基于模式选择信号确定多个发送流来继续处理数据。根据发送流的数量和模式选择信号，将编码数据转换成符号流，继续处理数据。基于模式选择信号启用多个RF发射机的数量，以将符号流中的相应一个码流转换为对应的RF信号，从而产生相应数量的RF信号。

42. 发明申请

US20050022090A1 Parallel concatenated code with soft-in soft-out interactive turbo decoder 有权
公开(公告)号：US20050022090A1
公开(公告)日：2005-01-27
申请号：US10897201
申请日：2004-07-22
申请人： Kelly Cameron , Hau Tran , Ba-Zhong Shen , Christopher Jones
发明人： Kelly Cameron , Hau Tran , Ba-Zhong Shen , Christopher Jones
IPC分类号： H03M13/15 , H03M13/25 , H03M13/27 , H03M13/29 , H03M13/41 , H03M13/45 , H04L1/00 , G06F7/00 , G06F17/30 , H03M13/00 , H04L5/12 , H04L23/02
CPC分类号： H03M13/3972 , H03M13/151 , H03M13/1515 , H03M13/25 , H03M13/258 , H03M13/27 , H03M13/2757 , H03M13/29 , H03M13/2966 , H03M13/2978 , H03M13/3905 , H03M13/3922 , H03M13/3927 , H03M13/3988 , H03M13/4107 , H03M13/6505 , H03M13/6561 , H04L1/0041 , H04L1/005 , H04L1/006 , H04L1/0065 , H04L1/0066 , H04L1/0068 , H04L1/0071
摘要： A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

43. 发明申请

US20060045213A1 Decoding error correcting codes transmitted through multiple wire twisted pair cables with uneven noise on the wires 有权
公开(公告)号：US20060045213A1
公开(公告)日：2006-03-02
申请号：US11172551
申请日：2005-06-30
申请人： Ba-Zhong Shen , Scott Powell , Kelly Cameron
发明人： Ba-Zhong Shen , Scott Powell , Kelly Cameron
IPC分类号： H04L27/06
CPC分类号： H04L1/0045 , H03M13/45 , H04L1/02 , H04L25/14 , H04L2001/0096
摘要： Decoding error correcting codes transmitted through multiple wire twisted pair cables with uneven noise on the wires. A novel approach is presented by which the metrics may be calculated for signals received over multi-wire (or alternatively referred to as multi-channel, and/or multi-path) communication channels to exploit an uneven distribution of noise among those wires for improved performance. In addition, this approach may also be performed in combination with employing an amplification factor to modify the metrics employed when performing ECC (Error Correcting Code) decoding. Moreover, when information is known concerning which 1 or more paths (e.g., wires) has an SNR that is different (e.g., lower in some cases) from the others, an even better adapted means of calculating the metrics associated with each of the paths (e.g., wires) may be employed to provide for improved performance with respect to iterative decoding processing of signals encoded using ECCs.

44. 发明申请

US20070162814A1 LDPC (low density parity check) code size adjustment by shortening and puncturing 失效
标题翻译：通过缩短和穿孔对LDPC（低密度奇偶校验）码大小进行调整
公开(公告)号：US20070162814A1
公开(公告)日：2007-07-12
申请号：US11417316
申请日：2006-05-03
申请人： Ba-Zhong Shen , Tak Lee , Kelly Cameron
发明人： Ba-Zhong Shen , Tak Lee , Kelly Cameron
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/1185 , H03M13/1188 , H03M13/618 , H03M13/6362
摘要： LDPC (Low Density Parity Check) code size adjustment by shortening and puncturing. A variety of LDPC coded signals may be generated from an initial LDPC code using selected shortening and puncturing. Using LDPC code size adjustment approach, a single communication device whose hardware design is capable of processing the original LDPC code is also capable to process the various other LDPC codes constructed from the original LDPC code after undergoing appropriate shortening and puncturing. This provides significant design simplification and reduction in complexity because the same hardware can be implemented to accommodate the various LDPC codes generated from the original LDPC code. Therefore, a multi-LDPC code capable communication device can be implemented that is capable to process several of the generated LDPC codes. This approach allows for great flexibility in the LDPC code design, in that, the original code rate can be maintained after performing the shortening and puncturing.
摘要翻译： LDPC（低密度奇偶校验）码字大小调整通过缩短和删截。可以使用选择的缩短和删截从初始LDPC码生成各种LDPC编码信号。使用LDPC码大小调整方法，硬件设计能够处理原始LDPC码的单个通信设备也能够在进行适当的缩短和删截之后处理由原始LDPC码构成的各种其他LDPC码。这提供了重要的设计简化和复杂性的降低，因为可以实现相同的硬件以适应从原始LDPC码产生的各种LDPC码。因此，可以实现能够处理几个所生成的LDPC码的具有多LDPC码的通信装置。这种方法允许在LDPC码设计中具有极大的灵活性，因为可以在执行缩短和删截之后维持原始码率。

45. 发明申请

US20050114748A9 Variable modulation with LDPC (low density parity check) coding 有权
标题翻译：具有LDPC（低密度奇偶校验）编码的可变调制
公开(公告)号：US20050114748A9
公开(公告)日：2005-05-26
申请号：US10669066
申请日：2003-09-23
申请人： Ba-Zhong Shen , Hau Thien Tran , Kelly Cameron
发明人： Ba-Zhong Shen , Hau Thien Tran , Kelly Cameron
IPC分类号： G11B20/18 , H03M13/11 , H03M13/25 , H03M13/29 , H03M13/41 , H03M13/45 , H04L1/00 , H04L1/16 , H04L27/18 , H04L27/26 , H03M13/00 , G06F11/00
CPC分类号： H03M13/6561 , G11B20/18 , G11B20/1833 , H03M13/11 , H03M13/1102 , H03M13/1105 , H03M13/25 , H03M13/255 , H03M13/256 , H03M13/258 , H03M13/27 , H03M13/2767 , H03M13/2771 , H03M13/2785 , H03M13/2957 , H03M13/4123 , H03M13/4161 , H03M13/45 , H03M13/6362 , H04L1/0041 , H04L1/0045 , H04L1/005 , H04L1/0058 , H04L1/006 , H04L1/0066 , H04L1/0068 , H04L1/0071 , H04L1/1671 , H04L27/18 , H04L27/2602
摘要： Variable modulation within combined LDPC (Low Density Parity Check) coding and modulation coding systems. A novel approach is presented for variable modulation encoding of LDPC coded symbols. In addition, LDPC encoding, that generates an LDPC variable code rate signal, may also be performed as well. The encoding can generate an LDPC variable code rate and/or modulation signal whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. Some embodiments employ a common constellation shape for all of the symbols of the signal sequence, yet individual symbols may be mapped according different mappings of the commonly shaped constellation; such an embodiment may be viewed as generating a LDPC variable mapped signal. In general, any one or more of the code rate, constellation shape, or mapping of the individual symbols of a signal sequence may vary as frequently as on a symbol by symbol basis.
摘要翻译：组合LDPC（低密度奇偶校验）编码和调制编码系统中的可变调制。提出了一种用于LDPC编码符号的可变调制编码的新颖方法。此外，也可以执行生成LDPC可变码率信号的LDPC编码。该编码可以生成其码率和/或调制可以像逐个符号一样频繁地变化的LDPC可变码率和/或调制信号。一些实施例对信号序列的所有符号采用公共星座形状，但是可以根据共同形状的星座图的不同映射来映射各个符号; 这样的实施例可以被视为生成LDPC可变映射信号。通常，信号序列的各个符号的码率，星座形状或映射中的任何一个或多个可以像逐个符号一样频繁地变化。

46. 发明申请

US20050268206A1 Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder 有权
标题翻译：支持LDPC（低密度奇偶校验）解码器中的位节点和校验节点处理的公共电路
公开(公告)号：US20050268206A1
公开(公告)日：2005-12-01
申请号：US11171568
申请日：2005-06-30
申请人： Hau Thien Tran , Kelly Cameron , Ba-Zhong Shen
发明人： Hau Thien Tran , Kelly Cameron , Ba-Zhong Shen
IPC分类号： G06K5/04 , G11B5/00 , G11B20/20 , H03M13/00 , H03M13/11 , H04L27/18 , H04L27/34
CPC分类号： H04L27/34 , H03M13/1117 , H03M13/112 , H03M13/1137 , H03M13/1165 , H03M13/658 , H04L27/18
摘要： Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a decoder may use the same circuitry to perform updating of edge messages with respect to bit nodes as well as updating of edge messages with respect to check nodes in the context of decoding LDPC coded signals. In addition, several very efficient architectures are presented to performing check node processing that involves the updating of edge messages with respect to check nodes. One embodiment performs check node processing using min** (min-double-star) processing in conjunction with min**− (min-double-star-minus) processing. Another embodiment performs check node processing using min†† (min-double-dagger) processing in conjunction with min†− (min-dagger-minus) processing. In addition, a single FIFO may be implemented to service a number of macro blocks in a parallel decoding implementation.
摘要翻译：支持LDPC（低密度奇偶校验）解码器中的位节点和校验节点处理的公共电路。提出了一种新颖的方法，其中解码器可以使用相同的电路来执行相对于位节点的边缘消息的更新，以及在解码LDPC编码信号的上下文中关于校验节点的边缘消息的更新。此外，提出了几个非常有效的架构来执行涉及到关于校验节点的边缘消息的更新的校验节点处理。一个实施例使用min **（min-double-star）处理结合min ** - （min-double-star-minus）处理来执行校验节点处理。另一个实施例使用min††（最小双匕首）处理结合最小† - （最小匕首 - 减号）处理来执行校验节点处理。此外，可以实现单个FIFO以在并行解码实现中服务多个宏块。

47. 发明申请

US20060085720A1 Message passing memory and barrel shifter arrangement in LDPC (Low Density Parity Check) decoder supporting multiple LDPC codes 审中-公开
标题翻译：消息传递存储器和桶形移位器布置在支持多个LDPC码的LDPC（低密度奇偶校验）解码器中
公开(公告)号：US20060085720A1
公开(公告)日：2006-04-20
申请号：US11171569
申请日：2005-06-30
申请人： Hau Thien Tran , Kelly Cameron , Ba-Zhong Shen
发明人： Hau Thien Tran , Kelly Cameron , Ba-Zhong Shen
IPC分类号： H03M13/00
CPC分类号： H03M13/658 , H03M13/1117 , H03M13/112 , H03M13/1137 , H03M13/1165
摘要： Message passing memory and barrel shifter arrangement in LDPC (Low Density Parity Check) decoder supporting multiple LDPC codes. A novel approach is presented by which a barrel shifter may be implemented in conjunction with a single message passing memory within an LDPC decoder. This arrangement also allows for a single bit/check processor to be employed that is operable to perform updating of edge messages with respect to check nodes as well as updating of edge messages with respect to bit nodes. There are a variety of embodiments by which the barrel shifter and the message passing memory may be implemented. By using this approach, a common architecture and design may operate to decode various types of LDPC coded signals including those whose code rate and/or modulation (including constellation shape and mapping) may vary as frequently as on a frame by frame basis or even on a block by block basis.
摘要翻译：消息传递存储器和桶形移位器布置在支持多个LDPC码的LDPC（低密度奇偶校验）解码器中。提出了一种新颖的方法，通过该方法可以结合在LDPC解码器内传递存储器的单个消息来实现桶形移位器。这种布置还允许采用单个位/检查处理器，该处理器可操作以相对于检查节点执行边缘消息的更新，以及相对于比特节点更新边缘消息。可以实现桶形移位器和消息传递存储器的各种实施例。通过使用这种方法，通常的架构和设计可以操作来解码各种类型的LDPC编码信号，包括其码率和/或调制（包括星座形状和映射）可能随着逐帧的变化而变化，或者甚至在逐块的基础。

48. 发明申请

US20060156206A1 Algebraic construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices 有权
公开(公告)号：US20060156206A1
公开(公告)日：2006-07-13
申请号：US11292135
申请日：2005-12-01
申请人： Ba-Zhong Shen , Joseph Lauer , Christopher Hansen , Kelly Cameron
发明人： Ba-Zhong Shen , Joseph Lauer , Christopher Hansen , Kelly Cameron
IPC分类号： H03M13/00
CPC分类号： H03M13/6362 , H03M13/1148 , H03M13/1151 , H03M13/116 , H03M13/1174 , H03M13/1177 , H03M13/1185 , H03M13/1188 , H03M13/1515 , H03M13/255
摘要： Algebraic method to construct LDPC (Low Density Parity Check) codes with parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. A novel approach is presented by which identity sub-matrices undergo cyclic shifting, thereby generating CSI sub-matrices that are arranged forming a parity check matrix of an LDPC code. The parity check matrix of the LDPC code may correspond to a regular LDPC code, or the parity check matrix of the LDPC code may undergo further modification to transform it to that of an irregular LDPC code. The parity check matrix of the LDPC code may be partitioned into 2 sub-matrices such that one of these 2 sub-matrices is transformed to be a block dual diagonal matrix; the other of these 2 sub-matrices may be modified using a variety of means, including the density evolution approach, to ensure the desired bit and check degrees of the irregular LDPC code.

49. 发明申请

US20070044001A1 Single stage implementation of min*, max*, min and/or max to perform state metric calculation in SISO decoder 审中-公开
标题翻译：单阶段实现min *，max *，min和/或max以在SISO解码器中执行状态度量计算
公开(公告)号：US20070044001A1
公开(公告)日：2007-02-22
申请号：US11543957
申请日：2006-10-05
申请人： Kelly Cameron , Thomas Hughes , Hau Tran
发明人： Kelly Cameron , Thomas Hughes , Hau Tran
IPC分类号： H03M13/00
CPC分类号： H03M13/3911 , H03M13/3905 , H03M13/395 , H04L1/005 , H04L1/0055
摘要： Single stage implementation of min*, max*, min and/or max to perform state metric calculation in soft-in soft-out (SISO) decoder. This allows for calculation of state metrics in an extremely efficient, fast manner. When performing min or max calculations, comparisons are made using 2 element combinations of the available inputs. Subsequently, logic circuitry employs the results of the 2 element comparisons the smallest (min) or largest (max) input. The max or min implementations may be employed as part of the max* and/or min* implementations. For max* and/or min* implementations, simultaneous calculation of appropriate values is performed while determining which input is the smallest or largest. Thereafter, the determination of which input is the smallest or largest is used to select the appropriate resultant value (of the values calculated) for max* and/or min*. Various degrees of precision are employed for the log correction values within the max* and/or min* implementations.
摘要翻译：单阶段实现min *，max *，min和/或max以在软中断（SISO）解码器中执行状态度量计算。这允许以非常有效，快速的方式计算状态度量。执行最小或最大计算时，使用可用输入的2个元素组合进行比较。随后，逻辑电路采用2元素比较最小（最小）或最大（最大）输入的结果。 max或min实现可以用作max *和/或min *实现的一部分。对于max *和/或min *实现，在确定哪个输入是最小或最大的时候执行适当值的同时计算。此后，使用哪个输入是最小或最大的确定来选择适用于max *和/或min *的合成结果值（所计算的值）。对于max *和/或min *实现中的对数校正值，采用了不同的精度。

50. 发明授权

US07080310B2 Forward error corrector 失效
公开(公告)号：US07080310B2
公开(公告)日：2006-07-18
申请号：US10733823
申请日：2003-12-11
申请人： Kelly Cameron
发明人： Kelly Cameron
IPC分类号： H03M13/00
CPC分类号： H03M13/153 , H03M13/1525 , H03M13/3746
摘要： A method for decoding an algebraic-coded message including determining a discrepancy indicator; determining an error locator polynomial according to a modified Berlekamp-Massey algorithm such that an uncorrectable message is detected; and producing a perceptible indication of the detected uncorrectable message. An apparatus includes storage devices, arithmetic components, and an uncorrectable message detector.

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