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41. 发明申请

US20090133003A1 COMMAND LANGUAGE FOR MEMORY TESTING 有权
标题翻译：用于记忆测试的命令语言
公开(公告)号：US20090133003A1
公开(公告)日：2009-05-21
申请号：US11944104
申请日：2007-11-21
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F9/45
CPC分类号： G06F11/27 , G06F8/41 , G11C29/16
摘要： A memory testing system for testing a plurality of memory locations in an electronic memory device is provided. The system includes a programmable memory device integrated into the electronic memory device capable of receiving and storing a compiled memory testing program. A processor is in communication with the programmable memory device to read and execute instructions from the compiled testing program stored in the programmable memory device and a command interpreter is configured to receive data from the processor related to commands to be executed during memory testing.
摘要翻译：提供了一种用于测试电子存储器件中的多个存储器位置的存储器测试系统。该系统包括集成到能够接收和存储编译的存储器测试程序的电子存储器件中的可编程存储器件。处理器与可编程存储器设备进行通信，以读取和执行存储在可编程存储器设备中的已编译测试程序的指令，并且命令解释器被配置为从存储器测试期间执行的命令接收来自处理器的数据。

42. 发明授权

US07313660B2 Data stream frequency reduction and/or phase shift 失效
标题翻译：数据流频率降低和/或相移
公开(公告)号：US07313660B2
公开(公告)日：2007-12-25
申请号：US10656195
申请日：2003-09-04
申请人： Alexander E. Andreev , Igor A. Vikhliantsev , Vojislav Vukovic
发明人： Alexander E. Andreev , Igor A. Vikhliantsev , Vojislav Vukovic
IPC分类号： G06F12/00
CPC分类号： H04L7/02 , H03M9/00 , Y10T436/143333
摘要： A frequency reduction or phase shifting circuit has an input receiving an input data stream having an input frequency and a representation of desired output frequency. A splitter splits the input data stream into a plurality of split signals each at a frequency of the desired output frequency. A plurality of catchers identify valid bits of each respective split signal. A shifter shifts valid bits identified by at least some of the catchers by a predetermined number, which establishes a de-serialization level for frequency reduction or phase shifting. An output provides an output data stream at the desired output frequency.
摘要翻译：频率降低或移相电路具有接收具有输入频率和所需输出频率的表示的输入数据流的输入。分流器将输入数据流分成多个分离信号，每个信号以期望的输出频率的频率分段。多个捕获器识别每个相应的分离信号的有效位。移位器将由至少一些捕获器识别的有效位移位预定数量，其建立用于频率降低或相移的解串级。输出以期望的输出频率提供输出数据流。

43. 发明授权

US07181563B2 FIFO memory with single port memory modules for allowing simultaneous read and write operations 有权
标题翻译：具有单端口存储器模块的FIFO存储器，用于允许同时的读写操作
公开(公告)号：US07181563B2
公开(公告)日：2007-02-20
申请号：US10692664
申请日：2003-10-23
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F12/00
CPC分类号： G06F12/06 , G06F5/14 , G06F5/16
摘要： The present invention is directed to a FIFO memory with single port memory modules that may allow simultaneous read and write operations. In an exemplary aspect of the present invention, a method for employing a FIFO memory with single port memory modules of half capacity to perform simultaneous read and write operations includes the following steps: (a) providing a first single port memory module for an even address of a read or write operation; (b) providing a second single port memory module for an odd address of a read or write operation; (c) alternating even address and odd address; and (d) when both a read request and a write request reach either the first single port memory module or the second single port memory module at a clock cycle, fulfilling the read request at the current clock cycle and fulfilling the write request at the next clock cycle.
摘要翻译：本发明涉及具有单端口存储器模块的FIFO存储器，其可以允许同时的读和写操作。在本发明的示例性方面，一种采用具有半容量的单端口存储器模块的FIFO存储器来执行同时读和写操作的方法包括以下步骤：（a）提供用于偶数地址的第一单端口存储器模块的读或写操作; （b）提供用于读或写操作的奇数地址的第二单端口存储器模块; （c）交替地址和奇地址; 和（d）当读请求和写请求都在时钟周期到达第一单端口存储器模块或第二单端口存储器模块时，在当前时钟周期满足读请求并在下一个时刻满足写请求时钟周期。

44. 发明授权

US07096413B2 Decomposer for parallel turbo decoding, process and integrated circuit 有权
标题翻译：并行turbo解码，处理和集成电路的分解器
公开(公告)号：US07096413B2
公开(公告)日：2006-08-22
申请号：US10299270
申请日：2002-11-19
申请人： Alexander E. Andreev , Ranko Scepanovic , Vojislav Vukovic
发明人： Alexander E. Andreev , Ranko Scepanovic , Vojislav Vukovic
IPC分类号： H03M13/03 , G06F11/00
CPC分类号： H03M13/6505 , H03M13/27 , H03M13/2957 , H03M13/6566
摘要： A decoder for access data stored in n memories comprises a function matrix containing addresses of the memory locations at unique coordinates. A decomposer sorts addresses from coordinate locations of first and second m×n matrices, such that each row contains no more than one address from the same memory. Positional apparatus stores entries in third and fourth m×n matrices identifying coordinates of addresses in the function matrix such that each entry in the third matrix is at coordinates that matches corresponding coordinates in the first matrix, and each entry in the fourth matrix is at coordinates that matches corresponding coordinates in the second matrix. The decoder is responsive to entries in the matrices for accessing data in parallel from the memories.
摘要翻译：用于存储在n个存储器中的访问数据的解码器包括在唯一坐标处包含存储器位置的地址的函数矩阵。分解器从第一和第二m×n矩阵的坐标位置排序地址，使得每行包含来自同一存储器的不超过一个地址。位置装置存储识别功能矩阵中地址的坐标的第三和第四m×n矩阵中的条目，使得第三矩阵中的每个条目在与第一矩阵中的对应坐标匹配的坐标处，并且第四矩阵中的每个条目在匹配的坐标处第二个矩阵中的对应坐标。解码器响应于矩阵中的条目，用于从存储器并行访问数据。

45. 发明授权

US07062726B2 Method for generating tech-library for logic function 失效
标题翻译：用于生成逻辑功能的技术库的方法
公开(公告)号：US07062726B2
公开(公告)日：2006-06-13
申请号：US10426549
申请日：2003-04-30
申请人： Alexander E. Andreev , Igor A. Vikhliantsev , Anatoli A. Bolotov
发明人： Alexander E. Andreev , Igor A. Vikhliantsev , Anatoli A. Bolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： The present invention is directed to a method for generating a tech-library for a logic function. A logic function has many representations. For each representation, a circuit for realizing the representation is decomposed into a combination of instances. An instance is a component logic circuit of a general logic circuit. There are pre-created tech-libraries for the instances. For example, a pre-created tech-library is created by categorizing tech-descriptions for primitive physical circuits based on a negation index. Thus, tech-descriptions for a circuit for realizing a representation are calculated from a combination of elements of the pre-created tech-libraries. Each calculated tech-description is compared with each existing element of a tech-library for the logic function. When a calculated tech-description has at least one marked parameter better or smaller than that of all existing elements of the tech-library for the logic function, the calculated tech-description is added to the tech-library. When the number of elements in the tech-library is at least twice larger than a limit, the number is reduced.
摘要翻译：本发明涉及一种用于生成用于逻辑功能的技术库的方法。逻辑函数有很多表示。对于每个表示，用于实现表示的电路被分解为实例的组合。实例是通用逻辑电路的分量逻辑电路。这些实例有预先创建的技术库。例如，通过基于否定索引对原始物理电路的技术描述进行分类来创建预先创建的技术库。因此，用于实现表示的电路的技术描述由预先创建的技术库的元素的组合计算。将每个计算的技术描述与逻辑功能的技术库的每个现有元素进行比较。当计算出的技术描述至少有一个比逻辑功能的技术库的所有现有元素更好或更小的标记参数时，计算出的技术描述被添加到技术库。当技术库中的元素数量至少比限制大两倍时，数量就会减少。

46. 发明授权

US07003510B2 Table module compiler equivalent to ROM 有权
公开(公告)号：US07003510B2
公开(公告)日：2006-02-21
申请号：US10177591
申请日：2002-06-19
申请人： Alexander E. Andreev , Ranko Scepanovic
发明人： Alexander E. Andreev , Ranko Scepanovic
IPC分类号： H03K19/20 , G06F17/50 , G06F17/30
CPC分类号： G06F17/5045 , Y10S707/99933
摘要： A method of constructing a circuit for a Boolean function includes receiving as input a Boolean function of a number n of input variables wherein the number n of input variables may be varied over a range; generating at least two intermediate functions comprising sub-functions of the Boolean function wherein zero or one is substituted for all but two of the number n of input variables; and generating a selected output of the Boolean function of the number n of input variables from only two of the intermediate functions.

47. 发明授权

US06691283B1 Optimization of comparator architecture 失效
标题翻译：比较器架构优化
公开(公告)号：US06691283B1
公开(公告)日：2004-02-10
申请号：US10017792
申请日：2001-12-12
申请人： Sergej B. Gashkov , Alexander E. Andreev , Aiguo Lu
发明人： Sergej B. Gashkov , Alexander E. Andreev , Aiguo Lu
IPC分类号： G06F1750
CPC分类号： G06F7/02 , G06F17/5045
摘要： A circuit embodied in an integrated circuit is characterized by an architecture having a minimal depth defined by a recursive expansion of output functions h_n=OR(h_k, AND(v_k, h_{n−k})) and v_n=AND(v_k, v{n−k}), where k=F_l and n−k=F_{l−1}, satisfies F_l
摘要翻译：具体化在集成电路中的电路的特征在于具有通过输出函数h_n = OR（h_k，AND（v_k，h_ {nk}））和v_n = AND（v_k，v_nk}）的递归展开定义的最小深度的架构 }），其中k = F_l和nk = F_ {1-1}，满足F_l

48. 发明授权

US06536027B1 Cell pin extensions for integrated circuits 失效
标题翻译：集成电路的单元针扩展
公开(公告)号：US06536027B1
公开(公告)日：2003-03-18
申请号：US09735837
申请日：2000-12-13
申请人： Mikhail I. Grinchuk , Alexander E. Andreev , Ranko Scepanovic
发明人： Mikhail I. Grinchuk , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A metal wire for a feature of a cell is extended using a grid based on a metal layer of the cell. Each grid element is assigned an “F” designator representing the metal wire being extended, an “E” designator representing blockages to extension of the metal wire, such as metal wires of other features, or a “U” designator representing grid elements that are neither F-designated, nor E-designated grid elements. U-designated grid elements that are neighbors to E-designated grid elements are identified. A minimum length path is defined through the U-designated grid elements that are not neighbors to E-designated grid elements between the cell boundary and a F-designated grid element.
摘要翻译：使用基于电池的金属层的栅格来延长用于电池特征的金属线。每个网格元素被分配一个表示正在扩展的金属线的“F”指示符，表示阻止金属线延伸的“E”指示符，例如其他特征的金属线，或表示网格元素的“U” F指定，E指定网格元素。与E指定的网格元素相邻的U指定网格元素被识别。通过U指定的网格元素定义最小长度路径，该网格元素不是单元格边界和F指定的网格元素之间的E指定网格元素的邻居。

49. 发明授权

US06292924B1 Modifying timing graph to avoid given set of paths 失效
标题翻译：修改时序图以避免给定的路径集
公开(公告)号：US06292924B1
公开(公告)日：2001-09-18
申请号：US08964997
申请日：1997-11-05
申请人： Ivan Pavisic , Anatoli A. Bolotov , Alexander E. Andreev , Ranko Scepanovic
发明人： Ivan Pavisic , Anatoli A. Bolotov , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Designing of the IC's require meeting real-world constraints such as minimization of the circuit area, minimization of wire length within the circuit, and minimization of the time the IC requires to perform its function, referred to as the IC delay. In order to design circuits to meet a given set of requirements, each signal path of the circuit must be analyzed. Because of the large number of the cells and the complex connections, the number of paths is very large and requires much computing power to analyze. Also, some of the paths are not important for the purposes of the operations of the chip and can be discounted during the analysis process. The present invention discloses a method and apparatus used to avoid analyzing non-important paths, referred to as false paths of a directed timing graph. To avoid the false paths, the timing graph representing the circuit is modified to exclude the false paths before the graph is analyzed. To modify the timing graph, duplicate nodes are constructed, duplicate edges are constructed, and some edges of the original graph are cut and replaced by mixed edges connecting non-duplicate nodes to duplicate nodes. Finally, mixed edges are created to connect duplicate nodes to non-duplicate nodes, integrating the duplicate graph with the original graph.
摘要翻译：集成电路芯片（IC）需要适当放置许多单元（电路组件组）和复杂的导线布线以连接单元的引脚。 IC的设计需要满足实际的限制，例如最小化电路面积，最小化电路内的电线长度，以及使IC执行其功能所需的时间最小化，称为IC延迟。为了设计电路以满足给定的一组要求，必须分析电路的每个信号路径。由于大量的单元和复杂的连接，路径数量非常多，需要很多计算能力进行分析。此外，一些路径对于芯片的操作的目的不重要，并且可以在分析过程期间被折扣。本发明公开了一种用于避免分析非重要路径的方法和装置，被称为定向定时图的假路径。为了避免错误路径，修改表示电路的时序图，以排除图表分析之前的虚假路径。为了修改时序图，构造了重复的节点，构建了重复的边，原始图的一些边被剪切，并将不重复的节点连接到重复节点的混合边替换。最后，创建混合边以将重复节点连接到非重复节点，将重复图与原始图集成。

50. 发明授权

US06247167B1 Method and apparatus for parallel Steiner tree routing 失效
标题翻译：并行Steiner树路由的方法和装置
公开(公告)号：US06247167B1
公开(公告)日：2001-06-12
申请号：US09062432
申请日：1998-04-17
申请人： Pedja Raspopovic , Ranko Scepanovic , Alexander E. Andreev
发明人： Pedja Raspopovic , Ranko Scepanovic , Alexander E. Andreev
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： The present invention provides for a method and apparatus to partition high fanout nets into smaller subnets. Said method includes the steps of identifying elementary pairs of pins in the net, each such elementary pair defining a line; eliminating lines such that a planar graph is formed; eliminating further lines such that a spanning tree is formed, said spanning tree connecting each pin in the net; identifying basic elements, each basic element forming a portion of said spanning tree; and constructing a connected cover for said net, said connected cover comprising a plurality of said basic elements.
摘要翻译：本发明提供了一种将高扇出网分成较小子网的方法和装置。所述方法包括以下步骤：识别网中的基本对引脚，每个这样的基本对定义一条线; 消除形成平面图形的线条; 消除形成生成树的更多的线，所述生成树连接网中的每个引脚; 识别基本元素，形成所述生成树的一部分的每个基本元素; 以及构建所述网的连接的盖，所述连接的盖包括多个所述基本元件。

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