专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US10165291B2 Parallel parsing in a video decoder 有权
公开(公告)号：US10165291B2
公开(公告)日：2018-12-25
申请号：US12929639
申请日：2011-02-04
申请人： Ola Hugosson , Dominic Hugo Symes
发明人： Ola Hugosson , Dominic Hugo Symes
IPC分类号： H04N19/436 , H04N19/172 , H04N19/44
摘要： A video decoder configured to decode an encoded video bitstream comprises a first parsing unit and a second parsing unit, each configured to independently parse the encoded video bitstream to derive parsing state information therefrom on which subsequent parsing of the encoded video bitstream at least partially depends and to identify macroblock information for decoding. The encoded video bitstream comprises frame header information defining a sequence of frames and each frame is composed of macroblocks represented by macroblock information. A control unit of the video encoder allocates each frame of macroblock information to one of the two parsing units to parse. The two parsing units are both configured to parse frame header information to thereby each derive parsing state information for the encoded video bitstream, and the two parsing unit are each configured to parse macroblock information allocated to them, skipping macroblock information allocated to the other parsing unit.

42. 发明申请

US20130246496A1 FLOATING-POINT VECTOR NORMALISATION 审中-公开
标题翻译：浮点矢量正则化
公开(公告)号：US20130246496A1
公开(公告)日：2013-09-19
申请号：US13825179
申请日：2011-03-14
申请人： Simon John Craske , Dominic Hugo Symes , Jorn Nystad
发明人： Simon John Craske , Dominic Hugo Symes , Jorn Nystad
IPC分类号： G06F17/10
CPC分类号： G06F17/10 , G06F5/012 , G06F7/483 , G06F7/5525 , G06F9/30036 , G06F2207/5521
摘要： When performing vector normalisation upon floating point values, an approximate reciprocal value generating instruction is used to generate an approximate reciprocal value with a mantissa of one and an exponent given by a bitwise inversion of the exponent field of the input floating point number. A modified number of multiplication instruction is used which performs a multiplication giving the standard IEEE 754 results other than when a signed zero is multiplied by a signed infinity which results a signed predetermined substitute value, such as 2. The normalisation operation may be performed by calculating a scaling value in dependence upon the vector floating point value using the approximate reciprocal value generating instruction. Each of the input components may then be scaled using the modify multiplication instruction to generate a scaled vector floating point value formed of a plurality of scaled components. The magnitude of the scaled vector floating point value can then be calculated and each of the individual scaled components divided by this magnitude to generate a normalised vector floating point value. The scaling value may be set to 2, where C is an integer value selected such that the sum of the squares of the plurality of scale components is less than a predetermined limit value.
摘要翻译：当在浮点值上执行向量归一化时，使用近似互逆值生成指令来生成一个尾数为1的近似互逆值，并且通过输入浮点数的指数字段的逐位反转给出的指数。使用修正数量的乘法指令，其执行给出标准IEEE 754结果的乘法，而不是当有符号零乘以带符号的无穷大，其产生诸如2的已签名的预定替代值。归一化操作可以通过计算根据使用近似互逆值生成指令的向量浮点值的缩放值。然后可以使用修改乘法指令来对每个输入分量进行缩放，以生成由多个缩放分量形成的缩放向量浮点值。然后可以计算缩放的向量浮点值的大小，并且每个单独的缩放的分量除以该大小以产生归一化的向量浮点值。缩放值可以被设置为2，其中C是选择的整数值，使得多个刻度分量的平方和小于预定极限值。

43. 发明申请

US20110206133A1 Parallel parsing in a video decoder 审中-公开
标题翻译：在视频解码器中并行解析
公开(公告)号：US20110206133A1
公开(公告)日：2011-08-25
申请号：US12929639
申请日：2011-02-04
申请人： Ola Hugosson , Dominic Hugo Symes
发明人： Ola Hugosson , Dominic Hugo Symes
IPC分类号： H04N7/26
CPC分类号： H04N19/436 , H04N19/172 , H04N19/44
摘要： A video decoder configured to decode an encoded video bitstream comprises a first parsing unit and a second parsing unit, each configured to independently parse the encoded video bitstream to derive parsing state information therefrom on which subsequent parsing of the encoded video bitstream at least partially depends and to identify macroblock information for decoding. The encoded video bitstream comprises frame header information defining a sequence of frames and each frame is composed of macroblocks represented by macroblock information. A control unit of the video encoder allocates each frame of macroblock information to one of the two parsing units to parse. The two parsing units are both configured to parse frame header information to thereby each derive parsing state information for the encoded video bitstream, and the two parsing unit are each configured to parse macroblock information allocated to them, skipping macroblock information allocated to the other parsing unit.
摘要翻译：被配置为解码编码视频比特流的视频解码器包括第一解析单元和第二解析单元，每个解析单元和第二解析单元被配置为独立地解析编码的视频比特流以从中导出解析状态信息，在该解码状态信息上编码视频比特流的后续解析至少部分地依赖于以识别用于解码的宏块信息。编码视频比特流包括定义帧序列的帧头信息，每帧由宏块信息表示的宏块组成。视频编码器的控制单元将每个宏块信息帧分配给两个解析单元之一进行解析。两个解析单元都被配置为解析帧头信息，从而各自导出编码视频比特流的解析状态信息，并且两个解析单元被配置为解析分配给它们的宏块信息，跳过分配给另一解析单元的宏块信息。

44. 发明申请

US20100217958A1 Address calculation and select-and-insert instructions within data processing systems 有权
标题翻译：数据处理系统中的地址计算和选择和插入指令
公开(公告)号：US20100217958A1
公开(公告)日：2010-08-26
申请号：US12662734
申请日：2010-04-30
申请人： Dominic Hugo Symes , Daniel Kershaw , Mladen Wilder
发明人： Dominic Hugo Symes , Daniel Kershaw , Mladen Wilder
IPC分类号： G06F9/30 , G06F9/315
CPC分类号： H03M13/4169 , G06F9/30036 , G06F9/345 , G06F9/355 , G06F9/3885 , G06F9/3887 , H04L1/0052 , H04L1/0054
摘要： A data processing system 2 is provided including an instruction decoder 34 responsive to program instructions within an instruction register 32 to generate control signals for controlling data processing circuitry 36. The instructions supported include an address calculation instruction which splits an input address value at a position dependent upon a size value into a first portion and second portion, adds a non-zero offset value to the first portion, sets the second portion to a value and then concatenates the result of the processing on the first portion and the second portion to form the output address value. Another type of instruction supported is a select-and-insert instruction. This instruction takes a first input value and shifts it by N bit positions to form a shifted value, selects N bits from within a second input value in dependence upon the first input value and then concatenates the shifted value with the N bits to form an output value. The address calculation instruction and the select-and-insert instruction described above are useful when manipulating two-dimensional data arrays, and particularly so when these are two-dimensional data arrays are formed of Viterbi trellis data through which traceback operations are to be performed.
摘要翻译：提供数据处理系统2，其包括响应于指令寄存器32内的程序指令的指令解码器34，以产生用于控制数据处理电路36的控制信号。所支持的指令包括地址计算指令，其将位置相关的输入地址值分割在将尺寸值分配到第一部分和第二部分中时，向第一部分添加非零偏移值，将第二部分设置为值，然后将处理结果连接在第一部分和第二部分上，以形成输出地址值。支持的另一种类型的指令是选择和插入指令。该指令采用第一输入值并将其移位N位位置以形成移位值，根据第一输入值从第二输入值内选择N位，然后将移位值与N位相连以形成输出值。上述地址计算指令和选择和插入指令在操纵二维数据阵列时非常有用，特别是当这些二维数据阵列由维特比网格数据形成时，通过该数据将执行回溯操作。

45. 发明授权

US07661104B2 Task following between multiple operating systems 有权
标题翻译：多个操作系统之间的任务
公开(公告)号：US07661104B2
公开(公告)日：2010-02-09
申请号：US10714482
申请日：2003-11-17
申请人： Simon Charles Watt , Christopher Bentley Dornan , Luc Orion , Nicolas Chaussade , Lionel Belnet , Stephane Eric Sebastian Brochier , David Hennah Mansell , Dominic Hugo Symes
发明人： Simon Charles Watt , Christopher Bentley Dornan , Luc Orion , Nicolas Chaussade , Lionel Belnet , Stephane Eric Sebastian Brochier , David Hennah Mansell , Dominic Hugo Symes
IPC分类号： G06F9/455 , G06F9/46 , G06F3/00 , H04L29/06
CPC分类号： G06F9/4812 , G06F9/526
摘要： A processor may utilise two operating systems (Non-Secure, Secure) between which calls may be made. In order that a second operating system can track task switches made by a first operating system, each time a call is made to the second operating system, this call includes an identifier to enable discrimination between the task which was executing on the first operating system when that call was made. The identifier can be a call identifier and/or a target thread identifier and may include further parameters.
摘要翻译：处理器可以利用两个可以进行呼叫的操作系统（非安全的，安全的）。为了使第二操作系统能够跟踪由第一操作系统进行的任务切换，每次对第二操作系统进行呼叫时，该呼叫包括标识符，以便能够在第一操作系统上执行的任务之间进行区分，那个电话是做的。标识符可以是呼叫标识符和/或目标线程标识符，并且可以包括其他参数。

46. 发明申请

US20090254736A1 Data processing system for performing data rearrangement operations 审中-公开
标题翻译：用于执行数据重排操作的数据处理系统
公开(公告)号：US20090254736A1
公开(公告)日：2009-10-08
申请号：US12078875
申请日：2008-04-07
申请人： Dominic Hugo Symes , Mladen Wilder
发明人： Dominic Hugo Symes , Mladen Wilder
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30036
摘要： An apparatus for processing data is provided comprising rearrangement circuitry having a plurality of rearrangement stages for rearranging a plurality N of input data elements, each rearrangement stage comprising at most N multiplexers arranged to select between M data elements where M is in integer less than N. Control circuitry is provided that is responsive to program instructions to control the rearrangement circuitry to perform rearrangement operations. The rearrangement circuitry is configurable by the control circuitry to perform a plurality of different rearrangement operations. The rearrangement circuitry comprises main rearrangement circuitry having a plurality of rearrangement stages in which there is a unique path between any given input element and any given output element and supplementary rearrangement circuitry in which from each input data element there is a path to at most C output data elements where 1
摘要翻译：提供了一种用于处理数据的装置，其包括具有多个重排级的重排电路，用于重新排列多个N个输入数据元素，每个重新排列级最多包括N个多路复用器，用于在M个小于N的整数M个数据元素之间进行选择。提供控制电路，其响应于程序指令来控制重排电路以执行重新排列操作。重排电路可由控制电路配置以执行多个不同的重排操作。重排电路包括具有多个重排阶段的主重排电路，其中在任何给定输入元件与任何给定输出元件和辅助重排电路之间存在唯一的路径，其中从每个输入数据元件到达至多C个输出的路径 1

47. 发明授权

US07448050B2 Handling multiple interrupts in a data processing system utilising multiple operating systems 有权
标题翻译：在使用多个操作系统的数据处理系统中处理多个中断
公开(公告)号：US07448050B2
公开(公告)日：2008-11-04
申请号：US10714484
申请日：2003-11-17
申请人： Simon Charles Watt , Christopher Bentley Dornan , Luc Orion , Nicolas Chaussade , Lionel Belnet , Stephane Eric Sebastien Brochier , Michael Robert Nonweiler , Dominic Hugo Symes
发明人： Simon Charles Watt , Christopher Bentley Dornan , Luc Orion , Nicolas Chaussade , Lionel Belnet , Stephane Eric Sebastien Brochier , Michael Robert Nonweiler , Dominic Hugo Symes
IPC分类号： G06F9/54 , G06F9/46
CPC分类号： G06F9/4812 , G06F9/45558 , G06F9/466 , G06F9/4843 , G06F21/6281 , G06F2009/45587
摘要： In a data processing system using multiple operating systems, an interrupt which itself may be interrupted by a subsequent interrupt which will be serviced in a different operating system, guards itself against being overlooked when that subsequent interrupt has been handled by starting a stub interrupt handling routine in that other operating system before executing the main handling routine in the originating operating system. Thus, the stub interrupt handling routine will be recognised in the other operating system irrespective of other interrupt events which may occur and accordingly the interrupted interrupt handling may be restarted.
摘要翻译：在使用多个操作系统的数据处理系统中，本身可能由将在不同的操作系统中被服务的后续中断中断的中断防止当通过启动存根中断处理程序来处理后续中断时被忽视在该起始操作系统中执行主处理例程之前的其他操作系统中。因此，在其他操作系统中将识别存根中断处理程序，而不管可能发生的其他中断事件如何，因此中断中断处理可能会重新启动。

48. 发明申请

US20080140750A1 Apparatus and method for performing rearrangement and arithmetic operations on data 有权
标题翻译：对数据执行重排和算术运算的装置和方法
公开(公告)号：US20080140750A1
公开(公告)日：2008-06-12
申请号：US11987323
申请日：2007-11-29
申请人： Daniel Kershaw , Mladen Wilder , Dominic Hugo Symes
发明人： Daniel Kershaw , Mladen Wilder , Dominic Hugo Symes
IPC分类号： G06F7/48 , G06F9/30
CPC分类号： G06F7/768 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3885 , G06F9/3887
摘要： An apparatus and method are provided for performing rearrangement operations and arithmetic operations on data. The data processing apparatus has processing circuitry for performing SIMD processing operations and scalar processing operations, a register bank for storing data and control circuitry responsive to program instructions to control the processing circuitry to perform data processing operations. The control circuitry is arranged to responsive to a combined rearrangement arithmetic instruction to control the processing circuitry to perform a rearrangement operation and at least one SIMD arithmetic operation on a plurality of data elements stored in the register bank. The rearrangement operation is configurable by a size parameter derived at least in part from the register bank. The size parameter provides an indication of a number of data elements forming a rearrangement element for the purposes of the rearrangement operation. The associated method involves controlling processing circuitry to perform a rearrangement operation and at least one SIMD arithmetic operation in response to a combined rearrangement arithmetic instruction and providing the scalar logic size parameter to configure the rearrangement operation. Computer program product is also provided comprising at least one combined rearrangement arithmetic instruction.
摘要翻译：提供了一种用于对数据执行重新排列操作和算术运算的装置和方法。数据处理装置具有用于执行SIMD处理操作和标量处理操作的处理电路，响应于程序指令来存储数据和控制电路的寄存器组，以控制处理电路执行数据处理操作。控制电路被布置为响应于组合重排算术指令来控制处理电路对存储在寄存器组中的多个数据元素执行重新排列操作和至少一个SIMD算术运算。重新布置操作可以由至少部分地从寄存器库导出的尺寸参数来配置。尺寸参数提供形成用于重排操作的重新排列元件的数量元素的数量的指示。相关联的方法涉及控制处理电路以响应于组合重排算术指令执行重排操作和至少一个SIMD算术运算，并提供标量逻辑大小参数以配置重新排列操作。还提供了包括至少一个组合重排算术指令的计算机程序产品。

49. 发明授权

US06687771B2 Parallel processing of multiple data values within a data word 有权
标题翻译：并行处理数据字中的多个数据值
公开(公告)号：US06687771B2
公开(公告)日：2004-02-03
申请号：US09769498
申请日：2001-01-26
申请人： Dominic Hugo Symes
发明人： Dominic Hugo Symes
IPC分类号： G06F748
CPC分类号： G06F7/544 , G06F5/00 , G06F2207/3808
摘要： An input data word contains multiple abutting input data values An. The input data word is split into two intermediate data words into which respective high order portions and low order portions of the data values are written spaced apart by vacant portions. Each intermediate data word may then be subject to one or more data processing operations with bits of the results extending into the vacant portions without corrupting adjacent data values. Finally, the intermediate data words may be recombined to produce result data values.
摘要翻译：输入数据字包含多个邻接输入数据值An。输入数据字被分成两个中间数据字，数据值的相应高阶部分和低阶部分被空出部分间隔开。然后可以对每个中间数据字进行一个或多个数据处理操作，其中结果的比特延伸到空的部分而不破坏相邻的数据值。最后，中间数据字可以被重组以产生结果数据值。

50. 发明授权

US06584532B1 Branch searching to prioritize received interrupt signals 失效
标题翻译：分支搜索优先接收中断信号
公开(公告)号：US06584532B1
公开(公告)日：2003-06-24
申请号：US09572729
申请日：2000-05-17
申请人： Hedley James Francis , Dominic Hugo Symes
发明人： Hedley James Francis , Dominic Hugo Symes
IPC分类号： G06F1326
CPC分类号： G06F13/26
摘要： A data processing system 2 for identifying the highest priority source signal from a plurality of signals each controlling the setting of a bit of a status word held within a status register 10 using programmable mask words. The mask words are used in a branch search strategy to successively narrow the possibilities for the highest priority bit at each search level until a single bit within the status word is identified corresponding to the highest priority interrupt signal. The programmable masks may be programmed for a particular configuration of the priorities of the respective bits within the status word. The branch search strategy provides a reduced maximum interrupt latency and improved predictability in the interrupt latency.
摘要翻译：一种数据处理系统2，用于从多个信号中识别最高优先级的源信号，每个信号使用可编程掩码字来控制状态寄存器10中保持的状态字的位的设置。在分支搜索策略中使用掩码字来连续地缩小每个搜索级别的最高优先级位的可能性，直到状态字中的单个位被识别为对应于最高优先级的中断信号。可编程掩模可以被编程用于状态字内各个位的优先级的特定配置。分支搜索策略提供了减少的最大中断延迟并提高了中断延迟的可预测性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式