专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US07050582B1 Pseudo-random one-to-one circuit synthesis 有权
标题翻译：伪随机一对一电路合成
公开(公告)号：US07050582B1
公开(公告)日：2006-05-23
申请号：US09883733
申请日：2001-06-18
申请人： Alexander E. Andreev , Igor A. Vikhliantsev , Ranko Scepanovic
发明人： Alexander E. Andreev , Igor A. Vikhliantsev , Ranko Scepanovic
IPC分类号： H04K1/00 , H04L9/00
CPC分类号： H04L9/0668
摘要： A method of defining a transformation between an input signal and an output signal. The transformation may implement a pseudo-random one-to-one function that may be implemented in hardware and/or software or modeled in software. The method may comprise the steps of (A) allocating the input signal among a plurality of block input signals, (B) establishing a plurality of transfer functions where each transfer function may be configured to present a plurality of unique symbols as a block output signal responsive to said block input signal, and (C) concatenating the block output signals to form the output signal.
摘要翻译：一种定义输入信号和输出信号之间变换的方法。该转换可以实现可以在硬件和/或软件中实现或以软件建模的伪随机一对一功能。该方法可以包括以下步骤：（A）在多个块输入信号之间分配输入信号，（B）建立多个传递函数，其中每个传递函数可被配置为呈现多个唯一符号作为块输出信号响应于所述块输入信号，以及（C）串联块输出信号以形成输出信号。

42. 发明授权

US06988252B2 Universal gates for ICs and transformation of netlists for their implementation 失效
标题翻译： IC的通用门户，以及网路数据库的实施转型
公开(公告)号：US06988252B2
公开(公告)日：2006-01-17
申请号：US10633856
申请日：2003-08-04
申请人： Alexander E. Andreev , Ranko Scepanovic
发明人： Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： An original netlist is transformed to one employing universal gates. A negation net is created for each net coupled to an input or output of each gate and an input of each inverter in the original net. Each gate is removed from the original netlist and a universal gate is inserted so that the nets previously coupled to the inputs and output of the removed gate and a negation of those nets are coupled to the inputs and outputs of the inserted universal gate in a selected arrangement. Each inverter is removed from the original netlist and the net previously coupled to the input of the inverter is negated. A universal gate comprises gates performing anding and oring functions whose inputs and outputs are selectively coupled to the nets of the original netlist, and their negations.
摘要翻译：一个原始网表被转换为一个采用通用门。针对耦合到每个门的输入或输出的每个网络以及原始网络中每个逆变器的输入产生一个否定网。每个门从原始网表移除，并且插入通用门，使得先前耦合到去除的门的输入和输出的网络以及这些网络的否定被耦合到所选择的插入的通用门的输入和输出安排。每个逆变器从原始网表中移除，并且先前耦合到逆变器输入端的网络被否定。通用门包括执行输入和输出功能的门，其输入和输出选择性地耦合到原始网表的网络，以及它们的否定。

43. 发明授权

US06941314B2 User selectable editing protocol for fast flexible search engine 有权
标题翻译：用户可选择的编辑协议，用于快速灵活的搜索引擎
公开(公告)号：US06941314B2
公开(公告)日：2005-09-06
申请号：US10123295
申请日：2002-04-15
申请人： Alexander E. Andreev , Ranko Scepanovic
发明人： Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F17/30327 , Y10S707/99937 , Y10S707/99942 , Y10S707/99943
摘要： A method of editing a sorted tree data structure includes selecting a minimum number of entries and a maximum number of entries in each vertex of the sorted tree data structure. If inserting an entry into a bottom vertex of the sorted tree data structure exceeds the maximum number of entries in the bottom vertex, then the entries are redistributed in the sorted tree data structure or a new bottom vertex is created so that no bottom vertex has more than the maximum number of entries and no fewer than the minimum number of entries. If deleting an entry from the bottom vertex results in fewer than the minimum number of entries, then the entries are redistributed in the sorted tree data structure or the bottom vertex is deleted so that no bottom vertex has fewer than the minimum number of entries and no bottom vertex has more than the maximum number of entries.
摘要翻译：编辑排序树数据结构的方法包括：选择排序树数据结构的每个顶点中的条目的最小数目和最大数目的条目。如果将条目插入到排序树数据结构的底部顶点超过底部顶点中的最大条目数，则条目将在排序的树数据结构中重新分布，或者创建一个新的底部顶点，以便底部顶点不再有比最大条目数不少于最小条目数。如果从底部顶点删除条目导致少于最小条目数，则条目将在排序的树数据结构中重新分配，或者删除底部顶点，以便没有底部顶点少于最小条目数，并且没有底部顶点具有多于最大条目数。

44. 发明授权

US06901571B1 Timing-driven placement method utilizing novel interconnect delay model 失效
标题翻译：利用新型互连延迟模型的定时驱动放置方法
公开(公告)号：US06901571B1
公开(公告)日：2005-05-31
申请号：US09010396
申请日：1998-01-21
申请人： Dusan Petranovic , Ranko Scepanovic , Ivan Pavisic
发明人： Dusan Petranovic , Ranko Scepanovic , Ivan Pavisic
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method for optimal placement of cells on a surface of an integrated circuit, comprising the steps of comparing a placement of cells to predetermined cost criteria and moving cells to alternate locations on the surface if necessary to satisfy the cost criteria. The cost criteria include a timing criterion based upon interconnect delay, where interconnect delay is modeled as a RC tree expressed as a function of pin-to-pin distance. The method accounts for driver to sink interconnect delay at the placement level, a novel aspect resulting from use of the RC tree model, which maximally utilizes available net information to produce an optimal timing estimate. Preferred versions utilize a RC tree interconnect delay model that is consistent with timing models used at design levels above placement, such as synthesis, and below placement, such as routing. Additionally, preferred versions can utilize either a constructive placement or iterative improvement placement method.
摘要翻译：一种用于在集成电路的表面上最佳地放置单元的方法，包括以下步骤：如果需要满足成本标准，将单元的布局与预定成本标准进行比较并将单元移动到表面上的替代位置。成本标准包括基于互连延迟的定时标准，其中互连延迟被建模为作为针对针距离的函数的RC树。该方法考虑了驱动程序以在布局级别中接收互连延迟，这是由使用RC树模型产生的新颖的方面，其最大限度地利用可用的网络信息来产生最佳的时序估计。首选版本使用RC树互连延迟模型，其与在布局之上的设计级别（例如合成）以及在布局之下（例如路由）使用的定时模型一致。另外，优选版本可以利用建设性位置或迭代改进放置方法。

45. 发明授权

US06845495B2 Multidirectional router 失效
标题翻译：多向路由器
公开(公告)号：US06845495B2
公开(公告)日：2005-01-18
申请号：US10027642
申请日：2001-12-20
申请人： Alexandre E. Andreev , Elyar E. Gasanov , Ranko Scepanovic
发明人： Alexandre E. Andreev , Elyar E. Gasanov , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： The present invention is directed to a system and method for providing multidirectional routing. The present invention may provide an arbitrary number of routing layers and an arbitrary direction on each of those layers to provide a smaller die size and to reduce power consumption by providing more flexibility for net routing directions.
摘要翻译：本发明涉及用于提供多向路由的系统和方法。本发明可以在这些层中的每一层上提供任意数量的路由层和任意方向，以提供更小的管芯尺寸，并通过为网络布线方向提供更多的灵活性来降低功耗。

46. 发明授权

US06662287B1 Fast free memory address controller 失效
标题翻译：快速可用内存地址控制器
公开(公告)号：US06662287B1
公开(公告)日：2003-12-09
申请号：US10000243
申请日：2001-10-18
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F1200
CPC分类号： G06F12/023 , Y10S707/99953 , Y10S707/99956
摘要： A memory manager for managing allocation of addresses in the memory is structured as a hierarchical tree having a top vertex, a bottom level and at least one intermediate level. The bottom level contains a plurality of bottom vertices each containing a plurality of representations of a Free or Taken status of respective addresses in the memory. Each intermediate contains at least one hierarchy vertex containing a plurality of labels such that each label is associated with a child vertex and defines whether or not a path that includes the respective child vertex ends in a respective bottom level vertex containing at least one Free representation. An allocation command changes the representation of the first Free address to Taken and a free command changes the representation of a specified address to Free. The labels in hierarchical vertices are changed to reflect the path conditions to the bottom vertices.
摘要翻译：用于管理存储器中的地址分配的存储器管理器被构造为具有顶部顶点，底部水平和至少一个中间水平的分层树。底层包含多个底部顶点，每个底部顶点包含多个存储器中相应地址的自由或取代状态的表示。每个中间体包含至少一个包含多个标签的层次顶点，使得每个标签与子顶点相关联，并且定义包含相应子顶点的路径是否包含在包含至少一个自由表示的相应底层顶点中。一个分配命令将第一个自由地址的表示更改为Taken，一个free命令将指定地址的表示更改为Free。更改层次顶点中的标签以反映底层顶点的路径条件。

47. 发明授权

US06324674B2 Method and apparatus for parallel simultaneous global and detail routing 失效
标题翻译：并行同时全局和细节路由的方法和装置
公开(公告)号：US06324674B2
公开(公告)日：2001-11-27
申请号：US09062309
申请日：1998-04-17
申请人： Alexander E. Andreev , Elyar E. Gasanov , Ranko Scepanovic , Pedja Raspopovic
发明人： Alexander E. Andreev , Elyar E. Gasanov , Ranko Scepanovic , Pedja Raspopovic
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A method for routing nets in an integrated circuit design, said method comprising the steps of dividing the integrated circuit design with lines in a first direction and lines in a second direction, forming a routing graph having vertices and edges, wherein vertices correspond to locations where lines in the first direction cross lines in the second direction, routing nets as a function of said routing graph with parallel processors operating substantially simultaneously, determining the relative wire congestion among different areas in the integrated circuit design, and rerouting nets passing though areas with a relatively high wire congestion.
摘要翻译：一种用于在集成电路设计中布线网络的方法，所述方法包括以下步骤：将集成电路设计与沿第一方向和第二方向的线分开，形成具有顶点和边缘的路由图，其中顶点对应于第一方向上的线在第二方向上交叉线，将并行网络作为所述路由图的函数，并行处理器基本上同时运行，确定集成电路设计中的不同区域之间的相对电线拥塞，以及重新路由通过区域的网络电线拥塞比较高

48. 发明授权

US06154874A Memory-saving method and apparatus for partitioning high fanout nets 失效
标题翻译：用于分割高扇出网络的存储器保存方法和装置
公开(公告)号：US06154874A
公开(公告)日：2000-11-28
申请号：US62219
申请日：1998-04-17
申请人： Ranko Scepanovic , Alexander E. Andreev , Pedja Raspopovic
发明人： Ranko Scepanovic , Alexander E. Andreev , Pedja Raspopovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： An object of the present invention is to provide for a method and apparatus to partition high fanout nets into smaller subnets. Said method includes the steps of identifying elementary pairs of pins in the net, each such elementary pair defining a line; eliminating lines such that a planar graph is formed; eliminating further lines such that a spanning tree is formed, said spanning tree connecting each pin in the net; identifying basic elements, each basic element forming a portion of said spanning tree; and constructing a connected cover for said net, said connected cover comprising a plurality of said basic elements. Said elementary pairs are identified by determining for each pin in said net a relative x-coordinate and a relative y-coordinate, constructing for each pin a combined binary coordinate as a function of the pin's relative x-coordinate and relative y-coordinate, ordering the pins in accordance with their respective combined binary coordinates, iteratively combining the pins until one pin remains, and iteratively expanding the pins.
摘要翻译：本发明的目的是提供一种将高扇出网分成较小子网的方法和装置。所述方法包括以下步骤：识别网中的基本对引脚，每个这样的基本对定义一条线; 消除形成平面图形的线条; 消除形成生成树的更多的线，所述生成树连接网中的每个引脚; 识别基本元素，形成所述生成树的一部分的每个基本元素; 以及构建所述网的连接的盖，所述连接的盖包括多个所述基本元件。通过确定所述网中的每个针的相对x坐标和相对的y坐标来识别所述基本对，所述相对的x坐标和相对的y坐标构成了作为销的相对x坐标和相对y坐标的函数的组合二进制坐标根据它们各自组合的二进制坐标的引脚，迭代地组合引脚直到保持一个引脚，并且迭代地扩展引脚。

49. 发明授权

US6038385A Physical design automation system and process for designing integrated circuit chip using "chessboard" and "jiggle" optimization 失效
标题翻译：物理设计自动化系统和使用“棋盘”和“抖动”优化设计集成电路芯片的过程
公开(公告)号：US6038385A
公开(公告)日：2000-03-14
申请号：US609397
申请日：1996-03-01
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev , Ivan Pavisic
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev , Ivan Pavisic
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A cell placement for an integrated circuit chip is divided into two "chessboard" patterns or "jiggles". Each pattern resembles a chessboard in that it consists of alternating regions of different types or "colors" such that no region of a given color has an edge common with another region of the same color. The jiggles are offset relative to each other such that the regions of one jiggle partially overlap at least two regions of the other jiggle. A placement improvement operation such as simulated annealing is performed sequentially for each color of each jiggle. During each operation, a plurality of parallel processors operate on the regions simultaneously using a previous copy of the entire chip, with one processor being assigned to one or more regions. At the end of each operation, the copy of the chip is updated. The chessboard patterns eliminate unproductive cell moves resulting from adjacent regions having a common edge. The jiggles enable cells to move to their optimal positions from their initial region to any other region on the chip. The regions can have rectangular, triangular or hexagonal shapes.
摘要翻译：集成电路芯片的单元布局分为两个“棋盘”图案或“跳棋”。每个图案类似于棋盘，其由不同类型或“颜色”的交替区域组成，使得给定颜色的区域不具有与相同颜色的另一区域相同的边缘。跳块相对于彼此偏移，使得一个颤动的区域部分地与另一个摇摆的至少两个区域重叠。针对每个抖动的每个颜色顺序地执行诸如模拟退火的放置改善操作。在每个操作期间，多个并行处理器使用整个芯片的先前副本同时在该区域上操作，一个处理器被分配给一个或多个区域。在每个操作结束时，更新芯片的副本。棋盘图案消除由具有共同边缘的相邻区域产生的非生产性细胞移动。这些跳跃使得电池从它们的初始区域移动到其最佳位置到芯片上的任何其它区域。这些区域可以具有矩形，三角形或六边形形状。

50. 发明授权

US5971588A Advanced modular cell placement system with optimization of cell neighborhood system 失效
标题翻译：先进的模块化放置系统，优化了小区邻域系统
公开(公告)号：US5971588A
公开(公告)日：1999-10-26
申请号：US672423
申请日：1996-06-28
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5072
摘要： A system for providing an optimal cluster of cells on the surface of a semiconductor chip is provided herein. The system collects a predetermined quantity of cells, this predetermined quantity containing a center cell, and all cells are assigned a distance value from the center cell. A coordinate is assigned to each cell based on its associated distance value, and new cell positions are calculated based on related cell positions and weights associated with each cell.
摘要翻译：本文提供了一种用于在半导体芯片的表面上提供最佳的单元簇的系统。系统收集预定量的单元，该预定量包含一个中心单元，并且从中心单元分配所有单元的距离值。基于其相关联的距离值将坐标分配给每个小区，并且基于与每个小区相关联的相关小区位置和权重来计算新的小区位置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式