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41. 发明授权

US08404544B1 Fabrication methods of integrated semiconductor structure 有权
标题翻译：集成半导体结构的制作方法
公开(公告)号：US08404544B1
公开(公告)日：2013-03-26
申请号：US13446769
申请日：2012-04-13
申请人： Jin-Mu Yin , Shyh-Wei Wang , Yen-Ming Chen
发明人： Jin-Mu Yin , Shyh-Wei Wang , Yen-Ming Chen
IPC分类号： H01L21/8234
CPC分类号： H01L21/28202 , H01L21/823842 , H01L21/823857 , H01L29/4975 , H01L29/518 , H01L29/66545 , H01L29/66553 , H01L29/78
摘要： A method for manufacturing the integrated circuit device comprises providing a substrate having a first region, a second region, and a third region. A first gate stack, a second gate stack, and a third gate stack are formed over the substrate in the first region, the second region, and the third region, respectively. The first gate stack, the second gate stack, and the third gate stack comprise a sacrificial layer over a first dielectric layer. The first gate stack and the second gate stack are removed and a second dielectric layer is formed in the first region and the second region. The portion of second dielectric layer in the first region is transformed into a third dielectric layer by a treatment.
摘要翻译：一种用于制造集成电路器件的方法包括提供具有第一区域，第二区域和第三区域的衬底。分别在第一区域，第二区域和第三区域中的衬底上形成第一栅极堆叠，第二栅极堆叠和第三栅极堆叠。第一栅极堆叠，第二栅极堆叠和第三栅极堆叠包括在第一介电层上的牺牲层。去除第一栅极堆叠和第二栅极堆叠，并且在第一区域和第二区域中形成第二电介质层。通过处理将第一区域中的第二电介质层的部分转变成第三电介质层。

42. 发明申请

US20110312145A1 SOURCE AND DRAIN FEATURE PROFILE FOR IMPROVING DEVICE PERFORMANCE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：用于改进装置性能的源和排出特征轮廓及其制造方法
公开(公告)号：US20110312145A1
公开(公告)日：2011-12-22
申请号：US12816519
申请日：2010-06-16
申请人： Ming-Huan Tsai , Chun-Fai Cheng , Hui Ouyang , Yuan-Hung Chiu , Yen-Ming Chen
发明人： Ming-Huan Tsai , Chun-Fai Cheng , Hui Ouyang , Yuan-Hung Chiu , Yen-Ming Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/66515 , H01L21/265 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.
摘要翻译：公开了一种用于制造集成电路器件的集成电路器件和方法。所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。掺杂区域注入与LDD区域相反的掺杂剂类型。

43. 发明授权

US07652893B2 Single or dual electronic package with footprint and pin sharing 有权
标题翻译：单或双电子封装，具有占位面积和引脚共享
公开(公告)号：US07652893B2
公开(公告)日：2010-01-26
申请号：US10908122
申请日：2005-04-28
申请人： Yen-Ming Chen
发明人： Yen-Ming Chen
IPC分类号： H05K1/18
CPC分类号： H05K1/181 , H05K3/3421 , H05K2201/09954 , H05K2201/10166 , H05K2201/10522 , Y02P70/611
摘要： A 6-pin electronic package includes a first side including a pair of first outer pins and a first middle pin, and a second side including a pair of second outer pins and a second middle pin. The first outer pins and the second middle pin are operatively coupled to a first circuit to provide a first function. The second outer pins and the first middle pin are operatively coupled to a second circuit to provide a second function. The 6-pin electronic package can be replaced on a circuit substrate with a first electronic package and a second electronic package that collectively include at least six pins. The 6-pin electronic package and the first and second electronic packages can be interchangeably used on a circuit substrate of an electronic device. The circuit substrate may include any one of the 6-pin electronic package mountable to the circuit substrate, and the first and second electronic packages. The first electronic package is mountable on the circuit substrate on a same footprint as the 6-pin electronic package. The second electronic package is mountable on the circuit substrate adjacent the first electronic package such that six pins of the first and second electronic packages share the same footprint as the pins of the 6-pin electronic package.
摘要翻译： 6引脚电子封装包括包括一对第一外部引脚和第一中间引脚的第一侧和包括一对第二外部引脚和第二中间引脚的第二侧。第一外部引脚和第二中间引脚可操作地耦合到第一电路以提供第一功能。第二外部引脚和第一中间引脚可操作地耦合到第二电路以提供第二功能。 6针电子封装可以在具有第一电子封装的电路基板上被替换，而第二电子封装共同包括至少六个引脚。 6针电子封装以及第一和第二电子封装可以互换地用于电子设备的电路基板上。电路基板可以包括可安装到电路基板的6针电子封装以及第一和第二电子封装中的任何一个。第一个电子封装以与6针电子封装相同的占位面安装在电路基板上。第二电子封装可安装在邻近第一电子封装的电路基板上，使得第一和第二电子封装的六个引脚与6针电子封装的引脚共用相同的封装。

44. 发明授权

US07468321B2 Application of impressed-current cathodic protection to prevent metal corrosion and oxidation 有权
标题翻译：应用电流阴极保护，防止金属腐蚀和氧化
公开(公告)号：US07468321B2
公开(公告)日：2008-12-23
申请号：US11382500
申请日：2006-05-10
申请人： Kai-Ming Ching , Chia-Fu Lin , Wen-Hsiang Tseng , Ta-Min Lin , Yen-Ming Chen , Hsin-Hui Lee , Chao-Yuan Su , Wen-Hsiang Tseng
发明人： Kai-Ming Ching , Chia-Fu Lin , Wen-Hsiang Tseng , Ta-Min Lin , Yen-Ming Chen , Hsin-Hui Lee , Chao-Yuan Su , Wen-Hsiang Tseng
IPC分类号： H01L21/44
CPC分类号： H01L23/544 , H01L21/76838 , H01L24/11 , H01L24/12 , H01L2223/54453 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/1147 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01051 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/01084 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/30105 , H01L2224/05647 , H01L2924/00014 , H01L2224/05671 , H01L2224/05124 , H01L2224/05147
摘要： A new method is provided for the processing of metals, most notably copper, such that damage to exposed surfaces of these metals is prevented. During a step of semiconductor processing, which results in exposing a metal surface to a wet substance having a pH value, a voltage is applied to the metal that is exposed. The value of the applied voltage can, dependent on the value of the pH constant of the wet substance, be selected such that the exposed metal surface is protected against alkaline effects of the wet substance.
摘要翻译：提供了一种新的方法来处理金属，特别是铜，以防止这些金属暴露表面的损坏。在半导体加工的步骤中，导致将金属表面暴露于具有pH值的湿物质的步骤中，向暴露的金属施加电压。施加电压的值可以根据湿物质的pH常数的值来选择，使得暴露的金属表面被保护免受湿物质的碱性影响。

45. 发明申请

US20070247370A1 Chip Antenna Apparatus for Receiving Global Positioning System Signals 失效
标题翻译：用于接收全球定位系统信号的芯片天线装置
公开(公告)号：US20070247370A1
公开(公告)日：2007-10-25
申请号：US11564067
申请日：2006-11-28
申请人： Chuan-Lin Hu , Yu-Wei Chen , Chang-Lun Liao , Shun-Tian Lin , Chang-Fa Yang , Yen-Ming Chen , Chao-Wei Wang
发明人： Chuan-Lin Hu , Yu-Wei Chen , Chang-Lun Liao , Shun-Tian Lin , Chang-Fa Yang , Yen-Ming Chen , Chao-Wei Wang
IPC分类号： H01Q1/38
CPC分类号： H01Q15/0006 , H01Q9/30
摘要： A chip antenna apparatus for receiving global positioning system signals, includes a L-shaped ground area and an omni-directional chip antenna. The L-shaped ground area is disposed on a circuit board. The omni-directional chip antenna is disposed in a gap of the L-shaped ground area on the circuit board and electrically connected to the L-shaped ground area.
摘要翻译：用于接收全球定位系统信号的芯片天线装置包括L形接地区域和全向芯片天线。 L形接地区域设置在电路板上。全向芯片天线设置在电路板上的L形接地区域的间隙中并电连接到L形接地区域。

46. 发明申请

US20070194996A1 Chip Antenna Mounting Apparatus 失效
标题翻译：芯片天线安装装置
公开(公告)号：US20070194996A1
公开(公告)日：2007-08-23
申请号：US11564033
申请日：2006-11-28
申请人： Chuan-Lin Hu , Yu-Wei Chen , Chang-Lun Liao , Shun-Tian Lin , Chang-Fa Yang , Yen-Ming Chen , Chao-Wei Wang
发明人： Chuan-Lin Hu , Yu-Wei Chen , Chang-Lun Liao , Shun-Tian Lin , Chang-Fa Yang , Yen-Ming Chen , Chao-Wei Wang
IPC分类号： H01Q1/24
CPC分类号： H01Q1/243 , H01Q1/125
摘要： A connection apparatus for a chip antenna includes a connection base and at least one chip slot. The connection base is disposed on a circuit board and connects to the electronic components of the circuit board via a connection wire. The chip slot is disposed on the connection base for inserting the chip antenna. Thus, the chip antenna is connected to the electronic components of the circuit board via the connection wire.
摘要翻译：用于芯片天线的连接装置包括连接基座和至少一个芯片槽。连接基座设置在电路板上，经由连接线与电路基板的电子部件连接。芯片槽设置在连接基座上，用于插入芯片天线。因此，芯片天线通过连接线连接到电路板的电子部件。

47. 发明申请

US20070028445A1 Fluxless bumping process 有权
标题翻译：无通风碰撞过程
公开(公告)号：US20070028445A1
公开(公告)日：2007-02-08
申请号：US11581122
申请日：2006-10-13
申请人： Chao-Yuan Su , Chia-Fu Lin , Hsin-Hui Lee , Yen-Ming Chen , Kai-Ming Ching , Li-Chih Chen , Wen-Chang Kuo , Yue-Ying Jian
发明人： Chao-Yuan Su , Chia-Fu Lin , Hsin-Hui Lee , Yen-Ming Chen , Kai-Ming Ching , Li-Chih Chen , Wen-Chang Kuo , Yue-Ying Jian
IPC分类号： B23K31/02
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/1147 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/0001 , H01L2924/01006 , H01L2924/01013 , H01L2924/01016 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , Y10T29/49144 , Y10T29/49146 , Y10T29/49147 , Y10T29/49149 , Y10T29/49179 , H01L2924/00014 , H01L2924/00
摘要： A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.
摘要翻译：一种方法，包括提供包括接合焊盘的半导体器件和覆盖在焊盘上的凸块下金属。在凸块下冶金上形成焊料结构，其中焊料结构包括包含氧化锡的外层。从CF 4和SF 6 6中的至少一个生成等离子体，并将焊料结构暴露于等离子体。加热焊料结构并对其进行冷却以在半导体器件上提供焊料凸块。

48. 发明授权

US07160811B2 Laminated silicate glass layer etch stop method for fabricating microelectronic product 有权
标题翻译：用于制造微电子产品的层压硅酸盐玻璃层蚀刻停止方法
公开(公告)号：US07160811B2
公开(公告)日：2007-01-09
申请号：US10278968
申请日：2002-10-22
申请人： Yen-Ming Chen , Huan-Chi Tseng , Yu-Hua Lee , Dian-Hau Chen , Chia-Hung Lai , Kang-Min Kuo
发明人： Yen-Ming Chen , Huan-Chi Tseng , Yu-Hua Lee , Dian-Hau Chen , Chia-Hung Lai , Kang-Min Kuo
IPC分类号： H01L21/302
CPC分类号： H01L21/31111 , H01L21/02129 , H01L21/02164 , H01L21/31612 , H01L21/31625 , H01L21/76801 , H01L21/823814 , H01L21/823835
摘要： A method for fabricating a microelectronic fabrication employs an undoped silicate glass layer as an etch stop layer when etching a doped silicate glass layer with an anhydrous hydrofluoric acid etchant. The method is particularly useful for forming a patterned salicide blocking dielectric layer when fabricating a complementary metal oxide semiconductor device.
摘要翻译：当用无水氢氟酸蚀刻剂蚀刻掺杂的硅酸盐玻璃层时，用于制造微电子制造的方法使用未掺杂的硅酸盐玻璃层作为蚀刻停止层。该方法在制造互补金属氧化物半导体器件时特别有用于形成图案化的自对准硅化物阻挡介电层。

49. 发明授权

US07091098B2 Semiconductor device with spacer having batch and non-batch layers 有权
标题翻译：具有间隔物的半导体器件具有批次和非批次层
公开(公告)号：US07091098B2
公开(公告)日：2006-08-15
申请号：US10819681
申请日：2004-04-07
申请人： Yen Ming Chen , Lin Jun Wu
发明人： Yen Ming Chen , Lin Jun Wu
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/6656 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device including a gate stack located over a substrate and a spacer located over the substrate and adjacent the gate stack. The spacer includes a plurality of layers, wherein at least one of the plurality of layers is a batch layer and at least one of the plurality of layers is a non-batch layer.
摘要翻译：一种半导体器件，其包括位于衬底上方的栅极堆叠和位于衬底上并且邻近栅极堆叠的间隔物。间隔物包括多个层，其中多个层中的至少一个层是批次层，并且多个层中的至少一个层是非批次层。

50. 发明授权

US06956292B2 Bumping process to increase bump height and to create a more robust bump structure 有权
标题翻译：凸起过程增加凸块高度并创建更坚固的凸块结构
公开(公告)号：US06956292B2
公开(公告)日：2005-10-18
申请号：US10613694
申请日：2003-07-03
申请人： Yang-Tung Fan , Cheng-Yu Chu , Fu-Jier Fan , Shih-Jane Lin , Chiou-Shian Peng , Yen-Ming Chen , Kuo-Wei Lin
发明人： Yang-Tung Fan , Cheng-Yu Chu , Fu-Jier Fan , Shih-Jane Lin , Chiou-Shian Peng , Yen-Ming Chen , Kuo-Wei Lin
IPC分类号： H01L21/60 , H01L23/48
CPC分类号： H01L24/11 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05171 , H01L2224/05572 , H01L2224/05644 , H01L2224/05655 , H01L2224/1147 , H01L2224/1191 , H01L2224/13099 , H01L2224/45144 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/014 , H01L2924/04941 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2224/05552 , H01L2924/00014 , H01L2924/013
摘要： A new process is provided which is an extension and improvement of present processing for the creation of a solder bump. After the layers of Under Bump Metal and a layer of solder metal have been created in patterned and etched format and overlying the contact pad, following a conventional processing sequence, a layer of polyimide is deposited. The solder flow is performed using the thickness of the deposited layer of polyimide to control the height of the column underneath the reflown solder.
摘要翻译：提供了一种新的工艺，其是用于产生焊料凸块的当前处理的延伸和改进。在图形化和蚀刻形式下形成了凹凸金属层和焊料金属层之后，按照传统的处理顺序，沉积了一层聚酰亚胺。使用聚酰亚胺沉积层的厚度来进行焊料流动，以控制在重熔焊料下面的柱的高度。

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