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41. 发明申请

US20160018449A1 ELECTRONIC DEVICE AND METHOD FOR TRACKING ENERGY CONSUMPTION 审中-公开
标题翻译：用于跟踪能量消耗的电子设备和方法
公开(公告)号：US20160018449A1
公开(公告)日：2016-01-21
申请号：US14868130
申请日：2015-09-28
申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH
发明人： Horst Diewald , Johann Zipperer , Peter Weber
IPC分类号： G01R21/00
CPC分类号： G01R21/00 , G01R21/007 , G01R22/10 , G06F1/26 , G06F1/28
摘要： The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least one inductor and a control block to keep the output voltage at a pre-selected level. The switching elements are configured to apply the source of energy to the inductors. The control block compares the output voltage of the energy tracking system to a reference value and controls the switching of the switched elements in order to transfer energy for the primary voltage into a secondary voltage at the output of the energy tracking system. The electronic device further comprises an ON-time and OFF-time generator and an accumulator wherein the control block is coupled to receive a signal from the ON-time and OFF-time generator and generates switching signals for the at least one switching element in the form of ON-time pulses with a constant ON-time.
摘要翻译：本发明涉及一种跟踪能量消耗的装置和方法。能量跟踪系统包括至少一个开关元件，至少一个电感器和控制块，以将输出电压保持在预选的电平。开关元件被配置为将电源施加到电感器。控制块将能量跟踪系统的输出电压与参考值进行比较，并控制开关元件的切换，以将能量跟踪系统的输出端的一次电压的能量传递到二次电压。电子设备还包括接通时间和关断时间发生器和累加器，其中控制块被耦合以从接通时间和断开时间发生器接收信号，并且生成用于所述至少一个开关元件的切换信号具有恒定导通时间的导通时间脉冲的形式。

42. 发明授权

US09230852B2 Integrated circuit (IC) having electrically conductive corrosion protecting cap over bond pads 有权
标题翻译：集成电路（IC），其在导体焊盘上具有导电腐蚀保护帽
公开(公告)号：US09230852B2
公开(公告)日：2016-01-05
申请号：US13775484
申请日：2013-02-25
申请人： Texas Instruments Incorporated , TEXAS INSTRUMENTS DEUTSCHLAND GmbH
发明人： Helmut Rinck , Fromund Metz , Jan Hermann Pape , Janet Riley
IPC分类号： H01L23/48 , H01L21/768 , H01L23/00 , H01L23/34 , H01L23/552 , H01L23/31 , H01L23/367
CPC分类号： H01L21/768 , H01L23/3171 , H01L23/34 , H01L23/367 , H01L23/3677 , H01L23/552 , H01L24/05 , H01L2224/05554 , H01L2924/1461 , H01L2924/00
摘要： An integrated circuit (IC) die has a top side surface providing circuitry including active circuitry configured to provide a function, including at least one bond pad formed from a bond pad metal coupled to a node in the circuitry. A dielectric passivation layer is over a top side surface of a substrate providing a contact area which exposes the bond pad. A metal capping layer includes an electrically conductive metal or an electrically conductive metal compound over at least the contact area to provide corrosion protection to the bond pad metal, which is in electrical contact with the bond pad metal. The metal capping layer can extend over structures other than the bond pads, such as to cover at least 80% of the area of the IC die to provide structures on the IC die protection from incident radiation.
摘要翻译：集成电路（IC）管芯具有顶侧表面提供电路，其包括被配置为提供功能的有源电路，所述功能包括由耦合到所述电路中的节点的接合焊盘金属片形成的至少一个接合焊盘。电介质钝化层位于衬底的顶侧表面上，提供暴露接合焊盘的接触区域。金属覆盖层包括在至少接触区域上的导电金属或导电金属化合物，以向与接合焊盘金属电接触的接合焊盘金属提供腐蚀保护。金属覆盖层可以在结合焊盘之外的结构上延伸，例如覆盖IC芯片的至少80％的面积，以提供IC芯片上的结构，防止入射辐射。

43. 发明申请

US20150333502A1 SHORT-CIRCUIT PROTECTION SYSTEM FOR POWER CONVERTERS 有权
标题翻译：电力转换器短路保护系统
公开(公告)号：US20150333502A1
公开(公告)日：2015-11-19
申请号：US14277294
申请日：2014-05-14
申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH
发明人： Franz Prexl , Mariangela De Martino
IPC分类号： H02H7/12 , H02M3/158
CPC分类号： H02H7/1213 , H02M1/36 , H02M3/158 , H02M3/1582 , H02M2001/325 , H02M2003/1566
摘要： One example includes a power converter system. The system includes a switching circuit configured to activate at least one power supply switch in response to a driver signal to provide an output voltage at an output based on an input voltage at an input and based on an inductor current associated with an inductor. The at least one power supply switch includes a parasitic diode that interconnects the inductor and the output. The system also includes a short-circuit protection system configured to detect a short-circuit condition and to deactivate the at least one power supply switch in response to the detection of the short-circuit condition to provide the inductor current from the inductor to the output through the parasitic diode in response to the deactivation of the at least one power supply switch.
摘要翻译：一个例子包括功率转换器系统。该系统包括开关电路，其配置为响应于驱动器信号激活至少一个电源开关，以基于输入处的输入电压并基于与电感器相关联的电感器电流在输出端提供输出电压。所述至少一个电源开关包括使电感器和输出互连的寄生二极管。该系统还包括短路保护系统，其被配置为检测短路状态，并且响应于短路状况的检测而停用至少一个电源开关，以将电感器电流从电感器提供给输出端响应于所述至少一个电源开关的去激活而通过所述寄生二极管。

44. 发明申请

US20150326419A1 RADIO SYSTEM FOR SIMULTANEOUS MULTI-CHANNEL RECEPTION 审中-公开
标题翻译：用于同时多通道接收的无线电系统
公开(公告)号：US20150326419A1
公开(公告)日：2015-11-12
申请号：US14272154
申请日：2014-05-07
申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH
发明人： Juergen MAYER-ZINTEL , Christian KELLER , Andreas HAGL
IPC分类号： H04L27/26
CPC分类号： H04B1/0014 , H04L5/06 , H04L27/2647 , H04L27/2653 , H04L27/2657
摘要： A radio communication system includes a frequency synthesizer, a radio frequency (RF) front end, a first receiver, and a second receiver. The frequency synthesizer is configured to generate an oscillation signal, and the RF front end is configured to receive a detected RF signal and apply the oscillation signal to downconvert the RF signal to an intermediate frequency (IF) signal. More particularly, the first receiver, coupled to the RF front end, is configured to extract, from the IF signal, information wirelessly transmitted by a first RF transmitter on a first frequency channel. The second receiver, coupled to the RF front end, is configured to extract, from the IF signal concurrently with the extraction of signal information by the first receiver, information wirelessly transmitted by a second RF transmitter on a second frequency channel.
摘要翻译：无线电通信系统包括频率合成器，射频（RF）前端，第一接收机和第二接收机。频率合成器被配置为产生振荡信号，并且RF前端被配置为接收检测到的RF信号并施加振荡信号以将RF信号下变频到中频（IF）信号。更具体地，耦合到RF前端的第一接收器被配置为从IF信号提取由第一频率信道上的第一RF发射机无线发送的信息。耦合到RF前端的第二接收器被配置为从第一接收机提取信号信息同时从IF信号提取由第二RF发射机在第二频率信道上无线发送的信息。

45. 发明授权

US09176188B2 Waveform calibration using built in self test mechanism 有权
标题翻译：使用内置自检机构进行波形校准
公开(公告)号：US09176188B2
公开(公告)日：2015-11-03
申请号：US14137994
申请日：2013-12-20
申请人： Texas Instruments Incorporated , Texas Instruments Deutschland GMBH
发明人： Sudipto Chakraborty , Jens Graul
IPC分类号： H04B3/46 , G01R31/317 , H04B17/00
CPC分类号： G01R31/31716 , G01R31/2822 , G01R31/3187 , H04B17/13 , H04B17/19
摘要： A system on a chip (SoC) includes a transceiver comprising a transmitter having a power amplifier and a receiver having a signal buffer. At least one of the transmitter and receiver has a configurable portion that can be configured to produce a range of waveforms (both in waveshape as well as duty cycle). A low cost built in self test (BIST) logic is coupled to the transceiver. The BIST logic is operable to calibrate the configurable portion of the transceiver to produce a waveform that has a selected harmonic component that has an amplitude that is less than a threshold value. Current consumed by the transceiver may be dynamically reduced by selecting an optimized waveform that has low harmonic components.
摘要翻译：芯片上的系统（SoC）包括收发器，包括具有功率放大器的发射机和具有信号缓冲器的接收机。发射器和接收器中的至少一个具有可配置部分，其可被配置为产生波形范围（波形以及占空比）。内置自检（BIST）逻辑的低成本耦合到收发器。 BIST逻辑可操作地校准收发器的可配置部分以产生具有小于阈值的幅度的选定谐波分量的波形。可以通过选择具有低谐波分量的优化波形来动态地减少收发器消耗的电流。

46. 发明申请

US20150301915A1 PROCESSOR WITH DEBUG PIPELINE 有权
标题翻译：处理器与调试管道
公开(公告)号：US20150301915A1
公开(公告)日：2015-10-22
申请号：US14255055
申请日：2014-04-17
申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH
发明人： Shrey Bhatia , Christian Wiencke , Armin Stingl , Ralph Ledwa , Wolfgang Lutsch
IPC分类号： G06F11/273
CPC分类号： G06F11/273 , G06F11/3024 , G06F11/3089 , G06F11/348 , G06F11/3636 , G06F11/3648 , G06F11/3656 , G06F11/3664 , Y02D10/34
摘要： A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.
摘要翻译：处理器包括包括多个执行阶段的执行流水线，执行流水线控制逻辑和调试系统。执行流水线控制逻辑被配置为控制通过执行阶段的指令的流程。调试系统包括调试管道和调试管道控制逻辑。调试流水线包括多个调试阶段。每个调试流水线阶段对应于执行流水线阶段，并且调试阶段的总数对应于执行阶段的总数。调试流水线控制逻辑耦合到执行流水线控制逻辑。调试流水线控制逻辑被配置为控制与指令相关联的调试信息的调试阶段的流程，并且将调试信息与执行流水线控制逻辑相对应地将调试信息推进到下一个调试阶段，以将指令推进到相应的阶段的执行管道。

47. 发明申请

US20150301830A1 PROCESSOR WITH VARIABLE PRE-FETCH THRESHOLD 审中-公开
标题翻译：具有可变预加工阈值的处理器
公开(公告)号：US20150301830A1
公开(公告)日：2015-10-22
申请号：US14255077
申请日：2014-04-17
申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH
发明人： Christian Wiencke , Johann Zipperer
IPC分类号： G06F9/38 , G06F9/30
摘要： A method and apparatus for controlling pre-fetching in a processor. A processor includes an execution pipeline and an instruction pre-fetch unit. The execution pipeline is configured to execute instructions. The instruction pre-fetch unit is coupled to the execution pipeline. The instruction pre-fetch unit includes instruction storage to store pre-fetched instructions, and pre-fetch control logic. The pre-fetch control logic is configured to fetch instructions from memory and store the fetched instructions in the instruction storage. The pre-fetch control logic is also configured to provide instructions stored in the instruction storage to the execution pipeline for execution. The pre-fetch control logic is further configured set a maximum number of instruction words to be pre-fetched for execution subsequent to execution of an instruction currently being executed in the instruction pipeline. The maximum number is based on a value contained in a pre-fetch threshold field of an instruction executed in the execution pipeline.
摘要翻译：一种用于在处理器中控制预取的方法和装置。处理器包括执行流水线和指令预取单元。执行流水线配置为执行指令。指令预取单元耦合到执行管线。指令预取单元包括存储预取指令的指令存储器和预取控制逻辑。预取控制逻辑被配置为从存储器获取指令并将获取的指令存储在指令存储器中。预取控制逻辑还被配置为将存储在指令存储器中的指令提供给执行管线以供执行。预取控制逻辑被进一步配置，在执行当前正在指令流水线中执行的指令之后，设置要预取的指令字的最大数量。最大数量是基于在执行管线中执行的指令的预取阈值字段中包含的值。

48. 发明授权

US09146263B2 Electronic device and method for tracking energy consumption 有权
标题翻译：用于跟踪能量消耗的电子装置和方法
公开(公告)号：US09146263B2
公开(公告)日：2015-09-29
申请号：US13788941
申请日：2013-03-07
申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH
发明人： Horst Diewald , Johann Zipperer , Peter Weber , Anton Brauchle
IPC分类号： G01R21/00 , G06F1/26 , G06F1/28 , G01R22/10
CPC分类号： G01R21/00 , G01R21/007 , G01R22/10 , G06F1/26 , G06F1/28
摘要： The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least one inductor and a control block to keep the output voltage at a pre-selected level. The switching elements are configured to apply the source of energy to the inductors. The control block compares the output voltage of the energy tracking system to a reference value and controls the switching of the switched elements in order to transfer energy for the primary voltage into a secondary voltage at the output of the energy tracking system. The electronic device further comprises an ON-time and OFF-time generator and an accumulator wherein the control block is coupled to receive a signal from the ON-time and OFF-time generator and generates switching signals for the at least one switching element in the form of ON-time pulses with a constant ON-time.
摘要翻译：本发明涉及一种跟踪能量消耗的装置和方法。能量跟踪系统包括至少一个开关元件，至少一个电感器和控制块，以将输出电压保持在预选的电平。开关元件被配置为将电源施加到电感器。控制块将能量跟踪系统的输出电压与参考值进行比较，并控制开关元件的切换，以将能量跟踪系统的输出端的一次电压的能量传递到二次电压。电子设备还包括接通时间和关断时间发生器和累加器，其中控制块被耦合以接收来自接通时间和断开时间发生器的信号，并且产生用于该至少一个开关元件的切换信号具有恒定导通时间的导通时间脉冲的形式。

49. 发明申请

US20150271913A1 ELECTRONIC DEVICE PACKAGE WITH VERTICALLY INTEGRATED CAPACITORS 审中-公开
标题翻译：具有垂直集成电容器的电子器件封装
公开(公告)号：US20150271913A1
公开(公告)日：2015-09-24
申请号：US14218523
申请日：2014-03-18
申请人： Texas Instruments Deutschland GmbH , Texas Instruments Incorporated
发明人： FRANK STEPNIAK , ANTON WINKLER
IPC分类号： H05K1/02 , H05K1/18
CPC分类号： H05K1/0231 , H05K1/0233 , H05K1/162 , H05K1/181 , H05K1/185 , H05K2201/1003
摘要： A system-in-a-package (SIP) has a semiconductor chip embedded in a dielectric substrate. An inductor is on a top surface of a substrate and is connected to the semiconductor chip. A thin film capacitor may be placed between the inductor and the dielectric substrate. A second thin film capacitor may be placed on the top surface of the semiconductor chip, or be embedded in the dielectric substrate with a thermal pad on a bottom surface of the substrate which is connected to the second thin film capacitor to facilitate heat dissipation.
摘要翻译：系统级封装（SIP）具有嵌入电介质基板中的半导体芯片。电感器位于衬底的顶表面上并连接到半导体芯片。电感器和电介质基片之间可以放置薄膜电容器。第二薄膜电容器可以放置在半导体芯片的顶表面上，或者在衬底的底表面上用热垫嵌入电介质衬底中，该衬垫连接到第二薄膜电容器以便于散热。

50. 发明申请

US20150171754A1 PRIMARY SIDE CURRENT REGULATION ON LLC CONVERTERS FOR LED DRIVING 有权
标题翻译：用于LED驱动的LLC转换器的主要电流调节
公开(公告)号：US20150171754A1
公开(公告)日：2015-06-18
申请号：US14133044
申请日：2013-12-18
申请人： Texas Instruments Deutschland GmbH
发明人： Roberto Scibilia
IPC分类号： H02M3/335 , H05B33/08
CPC分类号： H02M3/33507 , H02M3/3376 , H02M2001/0058 , H05B33/0815 , Y02B20/347 , Y02B20/348 , Y02B70/1433 , Y02B70/1491
摘要： An LLC converter, having a bridge circuit, coupled to an input voltage, comprising at least one pair of power switches, a resonant network, coupled to the bridge circuit and being driven by the at least one pair of power switches, an output transformer, coupled to the resonant network; the transformer having a first and a second primary side winding and at least a secondary side winding, a current sense transformer, coupled on the primary side in series to the resonant network and the first primary winding of the transformer, an integrator circuit coupled in parallel to the second primary side winding of the transformer and in parallel to the secondary side winding of the current sense transformer providing an integration of the voltage of the second primary side winding of the output transformer, a rectification circuit, coupled to the second primary side winding of the transformer, the transformer providing an output current of the LLC series resonant converter and a frequency adjustment controller, coupled to at least one pair of power switches and the current sense transformer and the integrator circuit providing driving signals to the at least one pair power switches.
摘要翻译：具有耦合到输入电压的桥式电路的LLC转换器包括耦合到桥式电路并由至少一对功率开关驱动的至少一对功率开关，谐振网络，输出变压器，耦合到谐振网络; 变压器具有第一和第二初级侧绕组和至少次级侧绕组，电流检测变压器，其耦合在初级侧，与谐振网络和变压器的第一初级绕组串联，并联耦合的积分器电路提供到变压器的第二初级侧绕组并且与电流检测变压器的次级侧绕组并联，提供输出变压器的第二初级侧绕组的电压的积分，整流电路，耦合到第二初级侧绕组所述变压器提供所述LLC串联谐振变换器的输出电流和耦合到至少一对功率开关的频率调节控制器，并且所述电流检测变压器和所述积分器电路向所述至少一对电力提供驱动信号开关。

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