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41. 发明专利

JPS5670412A MEASURING METHOD FOR FLOW RATE BY SEPARATOR AND METERING TANK 失效
公开(公告)号：JPS5670412A
公开(公告)日：1981-06-12
申请号：JP14821979
申请日：1979-11-14
申请人： YANO TOSHIO , TANAKA MAMORU
发明人： YANO TOSHIO , TANAKA MAMORU
IPC分类号： G01F1/00 , G01F1/30
摘要： PURPOSE:To shorten the time required for injection and enable measurement of large flow rate by a method wherein the flow-channel-shaped separator having, at the upper end thereof, a pair of sharp and parallel edges having a fixed from of cross section is passed linearly across the flow of the downstream part of a fluid at a fixed speed, while the fluid passing through the separator is injected into the metering tank and the flow rate is measured from the quantity of injection and the time for injection. CONSTITUTION:The separator 4 composed of a pair of separating plates 41 and 42 having, at the upper end thereof, a pair of sharp and parallel edges 411 and 421 having a fixed form of cross section and of side plates 43 and 44 is moved at a fixed speed across the fluid from one side to the other side e of the downstream part 7 shown by broken lines by a moving device 5 consisting of a driving part 51 and a connecting rod 52. Only the fluid passing through the separator 4 is injected into the metering tank 6. The time of for injection can be detected by a mechanical, electrical or optical method. Accordingly, the flow rate is found by dividing the quantity of injection by the time for injection. By this, the time for injection is shortened and thus the measurement of large flow rate can be performed.

42. 发明专利

JPS558135A REWRITABLE PROGRAMABLE LOGIC ARRAY 失效
公开(公告)号：JPS558135A
公开(公告)日：1980-01-21
申请号：JP8053178
申请日：1978-07-04
申请人： TANAKA MAMORU
发明人： TANAKA MAMORU
IPC分类号： G06F7/00 , G11C15/04 , H03K19/177
摘要： PURPOSE:To realize an optional logic function in a dynamic way as well as to secure memorization of the memory information with every word and bit by using only the simple and general-purpose current switching bistable memory cell for the intersection cell. CONSTITUTION:The rewritable programable logic array consists fundamentaly of retrieving circuit part 1 which carries out the operation of NOR (inversion + AND) or NAND (inversion + OR) plus reading circuit part 2 which performs also the NOR or NAND operation. Both circuits 1 and 2 feature the same components substantially and comprise selection circuits 13 and 23 which select and invert reading input signals 130 and 230 as well as writing input signals 131 and 231; retrieving array part 14 composed of the current switching memory cell groups existing at all intersections formed by sense driving paired lines 15 and 25 crossing designated lines 10 and 20; reading array part 24; and sensor driving circuit parts 16 and 26 connected to lines 15 and 25.

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