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41. 发明申请

US20090323394A1 PULSE RESET FOR NON-VOLATILE STORAGE 有权
标题翻译：非易失性存储器的脉冲复位
公开(公告)号：US20090323394A1
公开(公告)日：2009-12-31
申请号：US12339363
申请日：2008-12-19
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0007 , G11C7/12 , G11C7/22 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2013/0092 , G11C2213/32 , G11C2213/34 , G11C2213/71
摘要： A non-volatile storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits to SET and RESET the resistance-switching elements. The circuits that RESET the resistance-switching elements provide a pulse to the memory cells that is large enough in magnitude to SET and RESET the memory cells, and long enough to potentially RESET the memory cell but not long enough to SET the memory cells.
摘要翻译：非易失性存储系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储单元的三维存储器阵列（衬底上方），以及用于设置和复位电阻切换的电路元素。复位电阻切换元件的电路向存储器单元提供足够大的脉冲以设置和复位存储器单元，并且足够长以潜在地重置存储器单元，但不足以设置存储器单元。

42. 发明授权

US07633828B2 Hierarchical bit line bias bus for block selectable memory array 有权
标题翻译：块可选存储阵列的分层位线偏置总线
公开(公告)号：US07633828B2
公开(公告)日：2009-12-15
申请号：US11461362
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Luca G. Fasoli
发明人： Roy E. Scheuerlein , Luca G. Fasoli
IPC分类号： G11C8/00
CPC分类号： G11C16/08
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

43. 发明申请

US20090168480A1 Three dimensional hexagonal matrix memory array 有权
标题翻译：三维六边形矩阵记忆阵列
公开(公告)号：US20090168480A1
公开(公告)日：2009-07-02
申请号：US12005346
申请日：2007-12-27
申请人： Roy E. Scheuerlein , Christopher J. Petti
发明人： Roy E. Scheuerlein , Christopher J. Petti
IPC分类号： G11C5/02 , H01L21/308
CPC分类号： G03F7/2022 , B82Y10/00 , H01L27/0207 , H01L27/1021 , H01L27/112 , H01L27/224 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085
摘要： A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer.
摘要翻译：非易失性存储器件包括以基本上六边形图案布置的多个非易失性存储单元。非易失性存储单元可以是柱形非易失性存储单元，其可以使用三重或四重曝光光刻或通过使用自组装层进行图案化。

44. 发明申请

US20090166682A1 METHODS AND APPARATUS FOR FORMING MEMORY LINES AND VIAS IN THREE DIMENSIONAL MEMORY ARRAYS USING DUAL DAMASCENE PROCESS AND IMPRINT LITHOGRAPHY 有权
标题翻译：使用双重DAMASCENE过程和IMPRINT LITHOGRAPHY在三维存储器阵列中形成存储器线和VIAS的方法和装置
公开(公告)号：US20090166682A1
公开(公告)日：2009-07-02
申请号：US11967638
申请日：2007-12-31
申请人： ROY E. SCHEUERLEIN
发明人： ROY E. SCHEUERLEIN
IPC分类号： H01L27/10 , G03F1/00 , H01L21/311
CPC分类号： H01L21/48 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/31144 , H01L21/76807 , H01L21/76817 , H01L23/5384 , H01L27/10 , H01L27/101 , H01L2221/1021 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a damascene process. An imprint lithography mask for manufacturing a memory layer in a three dimensional memory is described. The mask includes a translucent material formed with features for making an imprint in a transfer material to be used in a damascene process, the mask having a plurality of imprint depths. At least one imprint depth corresponds to trenches for forming memory lines and at least one depth corresponds to holes for forming vias. Numerous other aspects are disclosed.
摘要翻译：本发明提供使用多深度压印光刻掩模和镶嵌工艺形成三维存储器阵列的系统，装置和方法。描述了用于制造三维存储器中的存储层的压印光刻掩模。掩模包括半透明材料，其形成有用于在用于镶嵌工艺中的转印材料中进行印记的特征，所述掩模具有多个印痕深度。至少一个压印深度对应于用于形成存储器线的沟槽，并且至少一个深度对应于用于形成通孔的孔。公开了许多其他方面。

45. 发明授权

US07542337B2 Apparatus for reading a multi-level passive element memory cell array 有权
标题翻译：用于读取多级无源元件存储单元阵列的装置
公开(公告)号：US07542337B2
公开(公告)日：2009-06-02
申请号：US11461343
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Tyler J. Thorp , Luca G. Fasoli
发明人： Roy E. Scheuerlein , Tyler J. Thorp , Luca G. Fasoli
IPC分类号： G11C16/04
CPC分类号： G11C11/56 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/77
摘要： A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10. The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current is sensed for at least two different combinations of reference current level and read bias voltage. A mid-level reference is used to read the LSB. When reading the MSB, a first reference between the 10 and 00 data states, and a second reference between 01 and 11 data states may be used, and the mid-level reference need not be used. In certain embodiments, the bit line current may be simultaneously compared against the first and second references, without requiring a delay to stabilize the bit line current to a different value, and the MSB generated accordingly.
摘要翻译：四级无源元件单元具有对应于降低电阻电平的存储器状态，其优选地分别映射到数据状态11,01,00和10. LSB和MSB优选地被映射为不同页面的一部分。为了区分存储单元状态，对于参考电流电平和读取偏置电压的至少两种不同的组合来检测所选择的位线电流。中间级参考用于读取LSB。当读取MSB时，可以使用10和00数据状态之间的第一个参考，并且可以使用01和11数据状态之间的第二个参考，并且不需要使用中间级参考。在某些实施例中，位线电流可以同时与第一和第二参考值进行比较，而不需要延迟来将位线电流稳定到不同的值，并且相应地生成MSB。

46. 发明申请

US20090086521A1 MULTIPLE ANTIFUSE MEMORY CELLS AND METHODS TO FORM, PROGRAM, AND SENSE THE SAME 审中-公开
标题翻译：多种抗体存储细胞及其形成，程序和感觉的方法
公开(公告)号：US20090086521A1
公开(公告)日：2009-04-02
申请号：US11864870
申请日：2007-09-28
申请人： S. Brad Herner , Roy E. Scheuerlein , Christopher J. Petti
发明人： S. Brad Herner , Roy E. Scheuerlein , Christopher J. Petti
IPC分类号： G11C5/06 , G11C17/06 , H01L21/44 , H01L29/00 , G11C17/18
CPC分类号： G11C17/16 , G11C11/5685 , G11C11/5692 , G11C13/0007 , G11C17/06 , G11C17/146 , G11C17/165 , G11C2213/32 , G11C2213/72 , H01L27/101 , H01L27/1021
摘要： Methods are described to fabricate, program, and sense a multilevel one-time-programmable memory cell including a steering element such as a diode and two, three, or more dielectric antifuses in series. The antifuses may be of different thicknesses, or may be formed of dielectric materials having different dielectric constants, or both. The antifuses and programming pulses are selected such that when the cell is programmed, the largest voltage drop in the memory cell is across only one of the antifuses, while the other antifuses allow some leakage current. In some embodiments, the antifuse with the largest voltage drop breaks down, while the other antifuses remain intact. In this way, the antifuses can be broken down individually, so a memory cell having two, three, or more antifuses may achieve any of three, four, or more unique data states.
摘要翻译：描述了制造，编程和感测多级一次可编程存储器单元的方法，所述存储单元包括诸如二极管的导向元件和串联的两个，三个或更多个介质反熔丝。反熔丝可以具有不同的厚度，或者可以由具有不同介电常数的介电材料或两者形成。选择反熔丝和编程脉冲，使得当单元被编程时，存储单元中的最大电压降仅跨越反熔丝中的一个，而另一个反熔丝允许一些漏电流。在一些实施例中，具有最大电压降的反熔丝分解，而其它反熔丝保持完整。以这种方式，可以单独地分解反熔丝，因此具有两个，三个或更多个反熔丝的存储单元可以实现三个，四个或更多个唯一数据状态中的任何一个。

47. 发明授权

US07499366B2 Method for using dual data-dependent busses for coupling read/write circuits to a memory array 有权
标题翻译：使用双数据相关总线将读/写电路耦合到存储器阵列的方法
公开(公告)号：US07499366B2
公开(公告)日：2009-03-03
申请号：US11461369
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Luca G. Fasoli
发明人： Roy E. Scheuerlein , Luca G. Fasoli
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/1048 , G11C7/18 , G11C8/08 , G11C8/14 , Y10T29/49002
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

48. 发明授权

US07495500B2 Method for using a multiple polarity reversible charge pump circuit 有权
标题翻译：使用多极性可逆电荷泵电路的方法
公开(公告)号：US07495500B2
公开(公告)日：2009-02-24
申请号：US11618838
申请日：2006-12-31
申请人： Ali K. Al-Shamma , Roy E. Scheuerlein
发明人： Ali K. Al-Shamma , Roy E. Scheuerlein
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , H02M2003/071 , H02M2003/077
摘要： A multiple polarity reversible charge pump circuit is disclosed which, in certain embodiments, may be configured to generate a positive voltage at times and may be reversed to generate a negative voltage at other times. Such a charge pump circuit is advantageous if both the positive and negative voltage are not simultaneously required. In certain other embodiments, a charge pump circuit generates a high output current for only a positive boosted voltage in one mode of operation, but lower current positive and negative boosted voltage outputs in another mode of operation. Use with certain erasable memory array technologies is disclosed, particularly certain resistive passive element memory cells, and more particularly in a three-dimensional memory array.
摘要翻译：公开了一种多极性可逆电荷泵电路，其在某些实施例中可被配置为有时产生正电压并且可以反向以在其它时间产生负电压。如果不同时需要正电压和负电压，则这种电荷泵电路是有利的。在某些其他实施例中，电荷泵电路仅在一种工作模式下产生仅仅正升压电压的高输出电流，而在另一种工作模式下产生较低电流正和负升压电压输出。公开了某些可擦除存储器阵列技术的使用，特别是某些电阻性无源元件存储单元，更具体地在三维存储器阵列中使用。

49. 发明申请

US20080310231A1 OPTIMIZATION OF CRITICAL DIMENSIONS AND PITCH OF PATTERNED FEATURES IN AND ABOVE A SUBSTRATE 有权
标题翻译：关键尺寸的优化和基板上及以上图案特征的优化
公开(公告)号：US20080310231A1
公开(公告)日：2008-12-18
申请号：US12136766
申请日：2008-06-10
申请人： James M. Cleeves , Roy E. Scheuerlein
发明人： James M. Cleeves , Roy E. Scheuerlein
IPC分类号： G11C11/34 , H01L27/092
CPC分类号： H01L27/105 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.
摘要翻译：在使用光刻和蚀刻技术的不同器件级别和那些器件级别的区域中，使用不同且优化的临界尺寸形成管芯。本发明的一个方面提供了形成在衬底上的存储器阵列，其中驱动电路形成在衬底中。存储器阵列的一个级别包括例如平行轨道和扇出区域。希望使轨道的密度最大化并最小化整个存储器阵列的光刻成本。这可以通过以比它下面的CMOS电路更紧的间距形成轨道来实现，从而允许在形成CMOS时使用更便宜的光刻工具，并且类似地通过优化用于器件级别的光刻和蚀刻技术以在轨道，并且在不太关键的扇出区域更放松。

50. 发明授权

US07463546B2 Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders 有权
标题翻译：使用包含可逆极性字线和位线解码器的无源元件存储器阵列的方法
公开(公告)号：US07463546B2
公开(公告)日：2008-12-09
申请号：US11461364
申请日：2006-07-31
申请人： Luca G. Fasoli , Christopher J. Petti , Roy E. Scheuerlein
发明人： Luca G. Fasoli , Christopher J. Petti , Roy E. Scheuerlein
IPC分类号： G11C8/00
CPC分类号： G11C17/18 , G11C8/08 , G11C8/10 , G11C17/16 , G11C17/165
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

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