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41. 发明授权

US06311267B1 Just-in-time register renaming technique 失效
标题翻译：即时注册重命名技术
公开(公告)号：US06311267B1
公开(公告)日：2001-10-30
申请号：US09196908
申请日：1998-11-20
申请人： Dung Quoc Nguyen , Hung Qui Le
发明人： Dung Quoc Nguyen , Hung Qui Le
IPC分类号： G06F938
CPC分类号： G06F9/384 , G06F9/3836 , G06F9/3855 , G06F9/3857
摘要： A target register of an instruction is assigned a rename register in response to the instruction being issued. That is, the target register is renamed at issue time, not at dispatch time. To handle a new deadlock issue this gives rise to, rename register allocation/deallocation logic, according to the present invention, includes logic for allocating and deallocating two sets of rename registers, one set from a regular rename buffer and another set from an overflow rename buffer. According to this allocation/deallocation logic, if the oldest dispatched, noncompleted instruction is ready for assignment of a rename register and the regular rename buffer is full, then a rename register is assigned from the overflow rename buffer to this instruction.
摘要翻译：指令的目标寄存器响应于正在发出的指令被分配重命名寄存器。也就是说，目标注册表在发布时更名，而不是在调度时间。为了处理新的死锁问题，这导致根据本发明重新命名寄存器分配/释放逻辑，包括用于分配和重新分配两组重命名寄存器的逻辑，一组来自常规重命名缓冲器，另一组来自溢出重命名缓冲。根据这种分配/释放逻辑，如果最旧的已分派的未完成指令准备好重新命名寄存器的分配，并且常规重命名缓冲区已满，则将重命名寄存器从溢出重命名缓冲区分配给该指令。

42. 发明授权

US06275918B1 Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator threshold 失效
标题翻译：从增加访问指示符阈值的数量获取历史表信息中的载入目标操作数预取地址
公开(公告)号：US06275918B1
公开(公告)日：2001-08-14
申请号：US09268307
申请日：1999-03-16
申请人： William Elton Burky , Peter Steven Lenk , Dung Quoc Nguyen , David Andrew Schroter , Shih-Hsiung Stephen Tung , Michael Thomas Vaden
发明人： William Elton Burky , Peter Steven Lenk , Dung Quoc Nguyen , David Andrew Schroter , Shih-Hsiung Stephen Tung , Michael Thomas Vaden
IPC分类号： G06F934
CPC分类号： G06F9/383 , G06F9/3455 , G06F9/3832
摘要： A method and system for improving pre-fetch accuracy in a data processing system utilizing a pre-fetch history table is disclosed. The method compares a portion of an instruction address to an address located as an entry in a pre-fetch history table based on the status of a validity bit contained in the entry. If the validity bit is set and the addresses match, an indicator field within the entry is checked to see if it is equal to or greater than a threshold level. When the indicator field is greater than the threshold level, a target operand address is pre-fetched based on stride and direction.
摘要翻译：公开了一种利用预取历史表改善数据处理系统中的预取精度的方法和系统。该方法基于条目中包含的有效位的状态，将指令地址的一部分与位于预取历史表中的条目的地址进行比较。如果有效位被设置并且地址匹配，则检查条目内的指示符字段以查看其是否等于或大于阈值级别。当指示符字段大于阈值电平时，将根据步幅和方向预取目标操作数地址。

43. 发明申请

US20150000909A1 COMPOSITIONS FOR OIL RECOVERY AND METHODS OF THEIR USE 有权
标题翻译：用于油料回收的组合物及其使用方法
公开(公告)号：US20150000909A1
公开(公告)日：2015-01-01
申请号：US14478491
申请日：2014-09-05
申请人： Aaron W. Sanders , Keith P. Johnston , Quoc Nguyen , Stephanie Adkins , Xi Chen , Ed G. Rightor
发明人： Aaron W. Sanders , Keith P. Johnston , Quoc Nguyen , Stephanie Adkins , Xi Chen , Ed G. Rightor
IPC分类号： C09K8/584 , E21B43/16
CPC分类号： C09K8/584 , C08G65/2609 , E21B43/16
摘要： Embodiments of the present disclosure include compositions for use in enhanced oil recovery, and methods of using the compositions for recovering oil. Compositions of the present disclosure include a nonionic, non-emulsifying surfactant having a CO2-philicity in a range of about 1.5 to about 5.0, carbon dioxide in a liquid phase or supercritical phase, and water, where the nonionic, non-emulsifying surfactant promotes a formation of a stable foam formed of carbon dioxide and water.
摘要翻译：本公开的实施方案包括用于增强油采收的组合物，以及使用该组合物回收油的方法。本公开的组合物包括在液相或超临界相中的二氧化碳在约1.5至约5.0的范围内的二氧化碳亲和性和非离子，非乳化表面活性剂促进的非离子型非乳化表面活性剂形成由二氧化碳和水形成的稳定泡沫的形成。

44. 发明申请

US20140140138A1 Three-Dimensional Flash Memory System 有权
标题翻译：三维闪存系统
公开(公告)号：US20140140138A1
公开(公告)日：2014-05-22
申请号：US13680719
申请日：2012-11-19
申请人： Hieu Van Tran , Hung Quoc Nguyen , Mark Reiten
发明人： Hieu Van Tran , Hung Quoc Nguyen , Mark Reiten
IPC分类号： G11C16/06
CPC分类号： G11C29/76 , G11C5/02 , G11C5/06 , G11C7/04 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C29/021 , G11C29/022 , G11C29/028 , G11C29/1201 , G11C29/26 , G11C2213/71 , H01L25/0652 , H01L25/18 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06541 , H01L2924/15311
摘要： A three-dimensional flash memory system is disclosed.
摘要翻译：公开了三维闪存系统。

45. 发明授权

US08705282B2 Mixed voltage non-volatile memory integrated circuit with power saving 有权
标题翻译：混合电压非易失性存储器集成电路，省电
公开(公告)号：US08705282B2
公开(公告)日：2014-04-22
申请号：US13286969
申请日：2011-11-01
申请人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
发明人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/30 , G11C5/147 , G11C11/5628 , G11C16/08
摘要： An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. A circuit that detects current flow from the second die pad is in the integrated circuit die. A switch is interposed between the first die pad and the first circuit to disconnect the first die pad from the first circuit in response to current flow detected by the circuit for detecting current flow.
摘要翻译：集成电路管芯具有用于接收第一电压的第一管芯焊盘和用于接收第二电压的第二管芯焊盘。第二电压小于第一电压。可在第一电压下操作的第一电路在集成电路管芯中。可在第二电压下操作的第二电路在集成电路管芯中，并连接到第二管芯焊盘。检测来自第二管芯焊盘的电流的电路在集成电路管芯中。开关被插入在第一管芯焊盘和第一电路之间，以响应于用于检测电流的电路检测到的电流来将第一管芯焊盘与第一电路断开。

46. 发明申请

US20130242672A1 Non-volatile Memory Device And A Method Of Operating Same 有权
标题翻译：非易失性存储器件及其操作方法相同
公开(公告)号：US20130242672A1
公开(公告)日：2013-09-19
申请号：US13419269
申请日：2012-03-13
申请人： Hieu Van Tran , Hung Quoc Nguyen , Nhan Do
发明人： Hieu Van Tran , Hung Quoc Nguyen , Nhan Do
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/0425 , G11C16/06 , G11C16/12 , G11C16/30 , G11C16/3418
摘要： An array of non-volatile memory cells in a semiconductor substrate of a first conductivity type. Each memory cell comprises first and second regions of a second conductivity type on a surface of the substrate, with a channel region therebetween. A word line overlies one portion of the channel region, is adjacent to the first region, and has little or no overlap with the first region. A floating gate overlies another portion of the channel region, and is adjacent to the first portion and the second region. A coupling gate overlies the floating gate. An erase gate overlies the second region. A bit line is connected to the first region. A negative charge pump circuit generates a negative voltage. A control circuit generates a plurality of control signals in response to receiving a command signal, and applies the negative voltage to the word line of unselected memory cells.
摘要翻译：在第一导电类型的半导体衬底中的非易失性存储单元阵列。每个存储单元包括在衬底的表面上的第二导电类型的第一和第二区域，其间具有沟道区域。字线重叠在通道区域的一部分上，与第一区域相邻，并且与第一区域几乎没有或没有重叠。浮动栅极覆盖沟道区域的另一部分，并且与第一部分和第二区域相邻。耦合栅极覆盖浮栅。擦除门覆盖第二区域。位线连接到第一区域。负电荷泵电路产生负电压。控制电路响应于接收到命令信号而产生多个控制信号，并将负电压施加到未选择存储单元的字线。

47. 发明授权

US08380964B2 Processor including age tracking of issue queue instructions 有权
标题翻译：处理器包括发布队列指令的年龄跟踪
公开(公告)号：US08380964B2
公开(公告)日：2013-02-19
申请号：US12417878
申请日：2009-04-03
申请人： James Wilson Bishop , Mary Douglass Brown , Jeffrey Carl Brownscheidle , Robert Allen Cordes , Maureen Anne Delaney , Jafar Nahidi , Dung Quoc Nguyen , Joel Abraham Silberman
发明人： James Wilson Bishop , Mary Douglass Brown , Jeffrey Carl Brownscheidle , Robert Allen Cordes , Maureen Anne Delaney , Jafar Nahidi , Dung Quoc Nguyen , Joel Abraham Silberman
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40
CPC分类号： G06F9/3855
摘要： An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store IDS. The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update. The issue queue may selectively clock a row and a column of cells of the age matrix that correspond to a dispatched instruction's queue position while leaving other cells unclocked to conserve power.
摘要翻译：信息处理系统包括具有可执行年龄跟踪操作的指令发布队列（IQ）的处理器。问题队列IQ维护或存储可能在内部数据存储IDS中发出无序的指令。 IDS组织了队列位置（QPOS）寻址布置中的指令。 IQ的年龄矩阵维护IDS内的这些指令的相对指令老化记录。年龄矩阵更新锁存器或其他存储单元数据，以反映在IQ调度操作期间IDS指令年龄的变化。在发送一个或多个指令期间，年龄矩阵可以仅更新需要数据改变的锁存器以反映改变的IDS指令年龄。年龄矩阵采用行和列数据和时钟控制来单独更新需要更新的锁存器。问题队列可以选择性地对与分派指令的队列位置相对应的年龄矩阵的一行和一列单元进行计时，同时使其他单元不被锁定以节省功率。

48. 发明授权

US08339187B2 Charge pump systems and methods 有权
公开(公告)号：US08339187B2
公开(公告)日：2012-12-25
申请号：US13070405
申请日：2011-03-23
申请人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
发明人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
IPC分类号： H02M3/18 , G05F3/20
CPC分类号： G05F3/02 , H02M3/073 , H02M2001/322
摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.

49. 发明授权

US08245018B2 Processor register recovery after flush operation 有权
标题翻译：冲洗操作后的处理器寄存器恢复
公开(公告)号：US08245018B2
公开(公告)日：2012-08-14
申请号：US12347924
申请日：2008-12-31
申请人： Dung Quoc Nguyen
发明人： Dung Quoc Nguyen
IPC分类号： G06F9/30
CPC分类号： G06F9/3844 , G06F9/3838 , G06F9/3863
摘要： An information handling system includes a processor that may perform general purpose register recovery operations after an instruction flush operation that an exception, such as a branch misprediction causes. The processor receives an instruction stream that may include multiple instructions that operate on a particular target register that stores instruction result information. The general purpose register may temporarily store instruction opcode and register bits information for use during dispatch, execution and other operations. The processor includes a recovery buffer unit for use during flush recovery operations. The processor may use recovery valid and recovery pending bits that correspond with each instruction during the register recovery from flush operation.
摘要翻译：信息处理系统包括处理器，其可以在诸如分支错误预测引起的异常的指令刷新操作之后执行通用寄存器恢复操作。处理器接收可以包括在存储指令结果信息的特定目标寄存器上操作的多个指令的指令流。通用寄存器可以临时存储在调度，执行和其他操作期间使用的指令操作码和寄存器位信息。处理器包括用于在冲洗恢复操作期间使用的恢复缓冲单元。处理器可以在刷新操作的寄存器恢复期间使用与每个指令对应的恢复有效和恢复挂起位。

50. 发明申请

US20120166787A1 ELECTRONIC DEVICE HAVING AN ALTERABLE CONFIGURATION AND METHODS OF MANUFACTURING AND CONFIGURING THE SAME 失效
标题翻译：具有可更换配置的电子设备及其制造和配置方法
公开(公告)号：US20120166787A1
公开(公告)日：2012-06-28
申请号：US13413974
申请日：2012-03-07
申请人： Robert Henderson Wood , Bao Quoc Nguyen
发明人： Robert Henderson Wood , Bao Quoc Nguyen
IPC分类号： G06F9/00 , G06F9/445 , G06F9/24
CPC分类号： G06F9/4401 , G06F9/441
摘要： An electronic device having an alterable configuration includes a non-volatile memory configurable to include at least a first partition and a second partition, the non-volatile memory storing a boot ROM. The boot ROM is operable when executed by a processor of said electronic device to, in the event that a third partition is available, boot an operating system in the third partition, the operating system operable when booted to cause the third partition to be deleted and the second partition to be expanded to encompass memory freed by the deletion; and otherwise boot an operating system in the first partition.
摘要翻译：具有可变配置的电子设备包括可配置为至少包括第一分区和第二分区的非易失性存储器，非易失性存储器存储引导ROM。当所述电子设备的处理器执行时，所述引导ROM可操作，以便在第三分区可用的情况下，引导所述第三分区中的操作系统，所述操作系统在被引导时可操作以使所述第三分区被删除，以及第二个分区被扩展以包含通过删除而释放的内存; 否则在第一个分区中引导操作系统。

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