专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2007010009A3 PERMANENT DATA HARDWARE INTEGRITY 审中-公开
标题翻译：永久数据硬件完整性
公开(公告)号：WO2007010009A3
公开(公告)日：2008-06-19
申请号：PCT/EP2006064425
申请日：2006-07-19
申请人： GEMPLUS CARD INT , BENOIT OLIVIER , TUNSTALL MICKAEL , QUOC NGUYEN KHANH
发明人： BENOIT OLIVIER , TUNSTALL MICKAEL , QUOC NGUYEN KHANH
IPC分类号： G06F11/10 , H03M13/05
CPC分类号： G06F11/10
摘要： The invention relates to the field of data securisation in an electronic component. The invention concerns a method for processing digital data X of an item of software that are coded on I x bits for detecting faults in an electronic circuit comprising at least one bus, a processing unit, a memory for running the software, and a hardware architecture provided to this end. The method comprises: a step for transforming the digital data X into digital data Z coded on l x + l y bits, the additional l y bits being the result of an integrity function f applied to said data X; a step for processing digital data Z by the set of hardware resources of the circuit, these hardware resources working on words l x + l y bits, and; at least one step for verifying the integrity of data Z during the processing step.
摘要翻译：本发明涉及电子元件中数据安全的领域。本发明涉及一种用于处理在I / O比特上编码的软件项的数字数据X的方法，用于检测电子电路中的故障，包括至少一个总线，处理单元，用于运行的存储器软件和为此提供的硬件架构。该方法包括：用于将数字数据X变换为以1×1×1×1位编码的数字数据Z的步骤，附加的I / 位是对所述数据X施加的完整性函数f的结果; 用于通过电路的硬件资源集合来处理数字数据Z的步骤，这些硬件资源用于处理单词1和/或更多位，以及; 在处理步骤期间验证数据Z的完整性的至少一个步骤。

2. 发明申请

WO2007010009A2 INTEGRITE MATERIELLE PERMANENTE DES DONNEES 审中-公开
标题翻译：永久数据硬件完整性
公开(公告)号：WO2007010009A2
公开(公告)日：2007-01-25
申请号：PCT/EP2006/064425
申请日：2006-07-19
申请人： GEMPLUS , BENOIT, Olivier , TUNSTALL, Mickael , QUOC NGUYEN, Khanh
发明人： BENOIT, Olivier , TUNSTALL, Mickael , QUOC NGUYEN, Khanh
CPC分类号： G06F11/10
摘要： La présente invention se rapporte au domaine de la sécurisation des données dans un composant électronique. La présente invention se rapporte à un procédé de traitement de données numériques X d'un logiciel codées sur Ix bits pour la détection de faute dans un circuit électronique comprenant au moins un bus, une unité de traitement et une mémoire pour l'exécution du logiciel et une architecture matérielle prévue à cet effet. Le procédé comprend : - une étape de transformation des données numériques X en des données numériques Z codées sur I x + l y bits, les l y bits additionnels étant le résultat d'une fonction f d'intégrité appliquée sur lesdites données X ; - une étape de traitement des données numériques Z par l'ensemble des ressources matérielles du circuit, ces ressources matérielles travaillant sur des mots de I x + l y bits ; - au moins une étape de vérification de l'intégrité desdites données Z pendant ladite étape de traitement .
摘要翻译：本发明涉及电子部件中的数据安全领域。本发明涉及一种用于处理编码在I比特上用于检测电子电路中的故障的软件项的数字数据X的方法，包括至少一个总线，处理单元，用于运行的存储器软件和为此提供的硬件架构。该方法包括：用于将数字数据X变换为以1×1×1×1位编码的数字数据Z的步骤，附加的1 / 位是对所述数据X施加的完整性函数f的结果; 用于通过电路的硬件资源集合来处理数字数据Z的步骤，这些硬件资源用于处理单词1和/或1个比特，以及在处理步骤期间验证数据Z的完整性的至少一个步骤。

3. 发明公开

US20230349568A1 ENERGY SAVING CONDITIONER AND HEAT SUPPLY METHOD 审中-公开
公开(公告)号：US20230349568A1
公开(公告)日：2023-11-02
申请号：US17801330
申请日：2020-11-12
申请人： Thinh Quoc Nguyen
发明人： Thinh Quoc Nguyen , Lam Thanh Doan
IPC分类号： F24F5/00 , F24T10/10
CPC分类号： F24F5/0046 , F24T10/10 , F24F2005/0057
摘要： The present disclosure provides an air conditioner comprising: an indoor heat exchanger to exchange heat between underground water and indoor air; an outdoor heat exchanger to exchange heat between underground water and outdoor air; a well; an underground water tank to store underground water; and a water pump to pump water from the well to the underground water tank. The indoor heat exchanger comprises a copper tube running through a row of parallel aluminum panels. Air is sucked by a fan through the indoor heat exchanger in the direction opposite to the underground water flow direction in the copper tube. Air is then passed through an evaporator unit of a compressor to be dehumidified. The underground water, after exchanging heat with the air to reach approximate room temperature, goes through a condensing unit of the compressor to release heat.

4. 发明申请

US20180352137A1 EVENT DATA AND LOCATION-LINKED SPHERICAL IMAGING SYSTEM 审中-公开
公开(公告)号：US20180352137A1
公开(公告)日：2018-12-06
申请号：US15995412
申请日：2018-06-01
申请人： Patrick A. St. Clair , Robert Adams DeRose , Gayle Fasoli DeRose , Viet Quoc Nguyen , Kenneth Nelson Gravenstede , Trevor Zachary DiMarco , Elyse M. DeRoo
发明人： Patrick A. St. Clair , Robert Adams DeRose , Gayle Fasoli DeRose , Viet Quoc Nguyen , Kenneth Nelson Gravenstede , Trevor Zachary DiMarco , Elyse M. DeRoo
IPC分类号： H04N5/232 , H04N5/265
摘要： An event data and location-linked spherical imaging system including a spherical imager configured for capturing a spherical image with an action; a localization device collocated with the spherical imager, the localization device configured for providing a location of the spherical imager; a level collocated with the spherical imager, the level configured for indicating an imaging level of the spherical imager; an event data receiver configured for receiving event data from a user, the event data is associated with one or more points of interest on the spherical image; and a compass configured for providing an orientation of the spherical imager in capturing the spherical image, wherein the orientation and location-linked event data is accessible within the context of the spherical image. In one embodiment, the spherical imager includes no more than two imagers. In one embodiment, the action is a single capture.

5. 发明授权

US09472284B2 Three-dimensional flash memory system 有权
标题翻译：三维闪存系统
公开(公告)号：US09472284B2
公开(公告)日：2016-10-18
申请号：US13680719
申请日：2012-11-19
申请人： Hieu Van Tran , Hung Quoc Nguyen , Mark Reiten
发明人： Hieu Van Tran , Hung Quoc Nguyen , Mark Reiten
IPC分类号： G11C11/34 , G11C16/06 , G11C5/02 , G11C5/06 , G11C16/30 , G11C29/26 , G11C16/04 , G11C16/26 , G11C7/04 , G11C29/02 , G11C29/12 , H01L25/065 , H01L25/18
CPC分类号： G11C29/76 , G11C5/02 , G11C5/06 , G11C7/04 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C29/021 , G11C29/022 , G11C29/028 , G11C29/1201 , G11C29/26 , G11C2213/71 , H01L25/0652 , H01L25/18 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06541 , H01L2924/15311
摘要： A three-dimensional flash memory system is disclosed.
摘要翻译：公开了三维闪存系统。

6. 发明授权

US08489863B2 Processor including age tracking of issue queue instructions 有权
标题翻译：处理器包括发布队列指令的年龄跟踪
公开(公告)号：US08489863B2
公开(公告)日：2013-07-16
申请号：US13451055
申请日：2012-04-19
申请人： James Wilson Bishop , Mary Douglass Brown , Jeffrey Carl Brownscheidle , Robert Allen Cordes , Maureen Anne Delaney , Jafar Nahidi , Dung Quoc Nguyen , Joel Abraham Silberman
发明人： James Wilson Bishop , Mary Douglass Brown , Jeffrey Carl Brownscheidle , Robert Allen Cordes , Maureen Anne Delaney , Jafar Nahidi , Dung Quoc Nguyen , Joel Abraham Silberman
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40
CPC分类号： G06F9/3855
摘要： An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store (IDS). The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update.
摘要翻译：信息处理系统包括具有可执行年龄跟踪操作的指令发布队列（IQ）的处理器。问题队列IQ维护或存储可能在内部数据存储（IDS）中发出无序的指令。 IDS组织了队列位置（QPOS）寻址布置中的指令。 IQ的年龄矩阵维护IDS内的这些指令的相对指令老化记录。年龄矩阵更新锁存器或其他存储单元数据，以反映在IQ调度操作期间IDS指令年龄的变化。在发送一个或多个指令期间，年龄矩阵可以仅更新需要数据改变的锁存器以反映改变的IDS指令年龄。年龄矩阵采用行和列数据和时钟控制来单独更新需要更新的锁存器。

7. 发明授权

US08488388B2 Method of programming a split gate non-volatile floating gate memory cell having a separate erase gate 有权
标题翻译：编程具有单独的擦除栅极的分离栅极非易失性浮动栅极存储单元的方法
公开(公告)号：US08488388B2
公开(公告)日：2013-07-16
申请号：US13286933
申请日：2011-11-01
申请人： Viktor Markov , Jong-Won Yoo , Hung Quoc Nguyen , Alexander Kotov
发明人： Viktor Markov , Jong-Won Yoo , Hung Quoc Nguyen , Alexander Kotov
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： G11C16/0416 , G11C16/3418 , H01L21/28273 , H01L29/42328
摘要： A non-volatile memory cell includes first and second regions and a channel region therebetween, a word line gate over a first portion of the channel region, a floating gate over another portion of the channel region and adjacent to the word line gate, a coupling gate over the floating gate, and an erase gate adjacent to the floating gate on an opposite side to the word line gate and over the second region. Programming the memory cell includes applying a first positive voltage to the word line gate, applying a voltage differential between the first and second regions, applying a second positive voltage to the coupling gate (where the voltages and the voltage differential are applied substantially at the same time), and applying a third positive voltage to the erase gate after a period of delay from the application of the first and second positive voltages and the voltage differential.
摘要翻译：非易失性存储单元包括第一和第二区域以及它们之间的沟道区域，沟道区域的第一部分上的字线栅极，沟道区域的另一部分上的浮动栅极，并且与字线栅极相邻，耦合在浮动栅极上方的栅极，以及与该字线栅极相反侧和第二区域上方的浮动栅极相邻的擦除栅极。对存储器单元进行编程包括对第一和第二区域施加第一正电压到第一和第二区域之间施加第一正电压，向耦合栅极施加第二正电压（其中施加电压和电压差异基本相同时间），并且在施加第一和第二正电压和电压差之后延迟一段时间后，向擦除栅极施加第三正电压。

8. 发明申请

US20130107631A1 Method Of Programming A Split Gate Non-volatile Floating Gate Memory Cell Having A Separate Erase Gate 有权
标题翻译：具有独立擦除门的分离门非易失性浮动栅极存储单元的编程方法
公开(公告)号：US20130107631A1
公开(公告)日：2013-05-02
申请号：US13286933
申请日：2011-11-01
申请人： Viktor Markov , Jong-Won Yoo , Hung Quoc Nguyen , Alexander Kotov
发明人： Viktor Markov , Jong-Won Yoo , Hung Quoc Nguyen , Alexander Kotov
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/3418 , H01L21/28273 , H01L29/42328
摘要： A non-volatile memory cell includes first and second regions and a channel region therebetween, a word line gate over a first portion of the channel region, a floating gate over another portion of the channel region and adjacent to the word line gate, a coupling gate over the floating gate, and an erase gate adjacent to the floating gate on an opposite side to the word line gate and over the second region. Programming the memory cell includes applying a first positive voltage to the word line gate, applying a voltage differential between the first and second regions, applying a second positive voltage to the coupling gate (where the voltages and the voltage differential are applied substantially at the same time), and applying a third positive voltage to the erase gate after a period of delay from the application of the first and second positive voltages and the voltage differential.
摘要翻译：非易失性存储单元包括第一和第二区域以及它们之间的沟道区域，沟道区域的第一部分上的字线栅极，沟道区域的另一部分上的浮动栅极，并且与字线栅极相邻，耦合在浮动栅极上方的栅极，以及与该字线栅极相反侧和第二区域上方的浮动栅极相邻的擦除栅极。对存储器单元进行编程包括对第一和第二区域施加第一正电压到第一和第二区域之间施加第一正电压，向耦合栅极施加第二正电压（其中施加电压和电压差异基本相同时间），并且在施加第一和第二正电压和电压差之后延迟一段时间后，向擦除栅极施加第三正电压。

9. 发明授权

US08354864B2 Sense amplifier for low voltage high speed sensing 有权
公开(公告)号：US08354864B2
公开(公告)日：2013-01-15
申请号：US13286166
申请日：2011-10-31
申请人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
发明人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
IPC分类号： G01R19/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

10. 发明申请

US20120260069A1 Processor Including Age Tracking of Issue Queue Instructions 有权
标题翻译：包括问题队列说明的年龄跟踪的处理器
公开(公告)号：US20120260069A1
公开(公告)日：2012-10-11
申请号：US13451055
申请日：2012-04-19
申请人： James Wilson Bishop , Mary Douglass Brown , Jeffrey Carl Brownscheidle , Robert Allen Cordes , Maureen Anne Delaney , Jafar Nahidi , Dung Quoc Nguyen , Joel Abraham Silberman
发明人： James Wilson Bishop , Mary Douglass Brown , Jeffrey Carl Brownscheidle , Robert Allen Cordes , Maureen Anne Delaney , Jafar Nahidi , Dung Quoc Nguyen , Joel Abraham Silberman
IPC分类号： G06F9/30
CPC分类号： G06F9/3855
摘要： An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store (IDS). The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update.
摘要翻译：信息处理系统包括具有可执行年龄跟踪操作的指令发布队列（IQ）的处理器。问题队列IQ维护或存储可能在内部数据存储（IDS）中发出无序的指令。 IDS组织了队列位置（QPOS）寻址布置中的指令。 IQ的年龄矩阵维护IDS内的这些指令的相对指令老化记录。年龄矩阵更新锁存器或其他存储单元数据，以反映在IQ调度操作期间IDS指令年龄的变化。在发送一个或多个指令期间，年龄矩阵可以仅更新需要数据改变的锁存器以反映改变的IDS指令年龄。年龄矩阵采用行和列数据和时钟控制来单独更新需要更新的锁存器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式