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41. 发明授权

US08772833B2 Power semiconductor device and fabrication method thereof 失效
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US08772833B2
公开(公告)日：2014-07-08
申请号：US13592560
申请日：2012-08-23
申请人： Woo Jin Chang , Jong Won Lim , Ho Kyun Ahn , Sang Choon Ko , Sung Bum Bae , Chull Won Ju , Young Rak Park , Jae Kyoung Mun , Eun Soo Nam
发明人： Woo Jin Chang , Jong Won Lim , Ho Kyun Ahn , Sang Choon Ko , Sung Bum Bae , Chull Won Ju , Young Rak Park , Jae Kyoung Mun , Eun Soo Nam
IPC分类号： H01L29/15
CPC分类号： H01L29/66901 , H01L29/2003 , H01L29/401 , H01L29/402 , H01L29/42316 , H01L29/66462 , H01L29/7786
摘要： Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.
摘要翻译：公开了功率半导体器件及其制造方法，其可以通过形成在栅电极和漏电极之间的场板来增加器件的击穿电压，并且同时实现更容易的制造工艺。根据本公开的示例性实施例的功率半导体器件包括形成在衬底上的源电极和漏电极; 形成在所述源电极和所述漏电极之间的电介质层具有比所述两个电极的高度低的高度，并且包括暴露所述衬底的蚀刻部分; 形成在蚀刻部分上的栅电极; 形成在栅电极和漏电极之间的电介质层上的场板; 以及配置成连接场板和源电极的金属。

42. 发明授权

US08518794B2 Semiconductor devices and methods of forming thereof 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US08518794B2
公开(公告)日：2013-08-27
申请号：US12874102
申请日：2010-09-01
申请人： Hokyun Ahn , Jong-Won Lim , Hyung Sup Yoon , Woojin Chang , Hae Cheon Kim
发明人： Hokyun Ahn , Jong-Won Lim , Hyung Sup Yoon , Woojin Chang , Hae Cheon Kim
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/8128 , H01L29/42316 , H01L29/66863
摘要： Provided is a semiconductor device. The semiconductor device includes: a substrate; an active layer on the substrate; a capping layer on the active layer; source/drain electrodes on the capping layer; a gate electrode on the active layer; and a first void region on a first sidewall of the gate electrode and a second void region on a second sidewall facing the first sidewall.
摘要翻译：提供一种半导体器件。半导体器件包括：衬底; 衬底上的有源层; 活性层上的覆盖层; 覆盖层上的源/漏电极; 有源层上的栅电极; 以及栅电极的第一侧壁上的第一空隙区域和面向第一侧壁的第二侧壁上的第二空隙区域。

43. 发明申请

US20130069127A1 FIELD EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20130069127A1
公开(公告)日：2013-03-21
申请号：US13556377
申请日：2012-07-24
申请人： Ho Kyun AHN , Jong-Won Lim , Sung Bum Bae , Sang Choon Ko , Young Rak Park , Woo Jin Chang , Jae Kyoung Mun , Eun Soo Nam , Jeong Jin Kim , Chull Won Ju
发明人： Ho Kyun AHN , Jong-Won Lim , Sung Bum Bae , Sang Choon Ko , Young Rak Park , Woo Jin Chang , Jae Kyoung Mun , Eun Soo Nam , Jeong Jin Kim , Chull Won Ju
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/7786 , H01L29/2003 , H01L29/402 , H01L29/42316 , H01L29/66462 , H01L29/66863 , H01L29/8128
摘要： A method for fabricating a field effect transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a cap layer, an ohmic metal layer and an insulating layer on a substrate; forming multilayered photoresists on the insulating layer; patterning the multilayered photoresists to form a photoresist pattern including a first opening for gate electrode and a second opening for field electrode; etching the insulating layer by using the photoresist pattern as an etching mask so that the insulating layer in the first opening is etched more deeply and the cap layer is exposed through the first opening; etching the cap layer exposed by etching the insulating layer through the first opening to form a gate recess region; and depositing a metal on the gate recess region and the etched insulating layer to form a gate-field electrode layer.
摘要翻译：根据本公开的示例性实施例的制造场效应晶体管的方法包括：在衬底上形成有源层，覆盖层，欧姆金属层和绝缘层; 在所述绝缘层上形成多层光致抗蚀剂; 图案化多层光致抗蚀剂以形成包括用于栅电极的第一开口和场电极的第二开口的光致抗蚀剂图案; 通过使用光致抗蚀剂图案作为蚀刻掩模来蚀刻绝缘层，使得第一开口中的绝缘层被更深地蚀刻并且盖层通过第一开口暴露; 通过蚀刻绝缘层通过第一开口蚀刻暴露的盖层，以形成栅极凹陷区域; 以及在所述栅极凹部区域和所述蚀刻绝缘层上沉积金属以形成栅极电极层。

44. 发明授权

US07970126B2 Communication terminal with movable display 有权
标题翻译：通讯终端带可移动显示
公开(公告)号：US07970126B2
公开(公告)日：2011-06-28
申请号：US11546352
申请日：2006-10-12
申请人： Sang Moon Ahn , Jong Won Lim
发明人： Sang Moon Ahn , Jong Won Lim
IPC分类号： H04M9/00 , H04M1/00
CPC分类号： H04M1/0295 , H04M1/0214 , H04M1/0235
摘要： A communication terminal equipped with a sliding-type flat display module includes a main body and a flat display which slides between retracted and extended positions along a first axis relative to the main body and which rotates to a tilted position along a second axis when in the extended position. The first axis may be substantially perpendicular to the second axis. In the retracted position, the flat display is unable to rotate to the tilted position along the second axis. Also, in this position, the display is partially visible to allow information to be read by a user while at the same time being protected within a receiving part of the terminal.
摘要翻译：具有滑动型平板显示模块的通信终端包括主体和平面显示器，其在相对于主体的第一轴线的缩回位置和延伸位置之间滑动，并且当在第二轴线处于第二轴线时旋转到倾斜位置延长位置第一轴线可以基本上垂直于第二轴线。在缩回位置，平面显示器不能沿着第二轴线旋转到倾斜位置。此外，在该位置，显示器是部分可见的，以允许用户读取信息，同时在终端的接收部分内被保护。

45. 发明授权

US07679105B2 Hetero junction bipolar transistor and method of manufacturing the same 失效
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US07679105B2
公开(公告)日：2010-03-16
申请号：US11634614
申请日：2006-12-06
申请人： Yong Won Kim , Eun Soo Nam , Ho Young Kim , Sang Seok Lee , Dong Suk Jun , Hong Yeol Lee , Seon Eui Hong , Dong Young Kim , Jong Won Lim , Myoung Sook Oh
发明人： Yong Won Kim , Eun Soo Nam , Ho Young Kim , Sang Seok Lee , Dong Suk Jun , Hong Yeol Lee , Seon Eui Hong , Dong Young Kim , Jong Won Lim , Myoung Sook Oh
IPC分类号： H01L29/24
CPC分类号： H01L29/7371 , H01L29/0817 , H01L29/41708 , H01L29/66318
摘要： Provided are a hetero-junction bipolar transistor (HBT) that can increase data processing speed and a method of manufacturing the hetero-junction bipolar transistor. The HBT includes a semi-insulating compound substrate, a sub-collector layer formed on the semi-insulating compound substrate, a pair of collector electrodes disposed at a predetermined distance apart from each other on a predetermined portion of the sub-collector layer, a collector layer and a base layer disposed between the collector electrodes, a pair of base electrodes disposed at a predetermined distance apart from each other on a predetermined portion of the base layer, an emitter layer stack disposed between the base electrodes, and an emitter electrode that is formed on the emitter layer stack, and includes a portion having a line width wider than the line width of the emitter layer stack, wherein both sidewalls of the emitter electrode are respectively aligned with inner walls of the pair of base electrodes, and sidewalls of the collector layer and the base layer are located between outer sidewalls of the pair of base electrodes of the pair of base electrodes.
摘要翻译：提供了可以提高数据处理速度的异质结双极晶体管（HBT）和制造异质结双极晶体管的方法。 HBT包括半绝缘复合基板，形成在半绝缘复合基板上的副集电极层，在副集电极层的预定部分上彼此隔开预定距离设置的一对集电极，集电极层和设置在集电极之间的基极层，在基极层的预定部分上彼此隔开预定距离设置的一对基底电极，设置在基极之间的发射极层叠层和发射极电极，形成在发射极层堆叠上，并且包括具有比发射极层堆叠的线宽宽的线宽的部分，其中发射极电极的两个侧壁分别与一对基底电极的内壁对齐，并且侧壁集电极层和基极层位于该对基极的一对基极的外侧壁之间。

46. 发明申请

US20090242375A1 COMMUNICATION TERMINAL HAVING HOUSING WITH KEY BUTTONS COUPLED THERETO 有权
标题翻译：具有与其连接的键钮的外壳的通信终端
公开(公告)号：US20090242375A1
公开(公告)日：2009-10-01
申请号：US12409720
申请日：2009-03-24
申请人： Tae Hyun Kim , Kyung Soo Ji , Jong Won Lim
发明人： Tae Hyun Kim , Kyung Soo Ji , Jong Won Lim
IPC分类号： H01H13/76 , H01H13/70
CPC分类号： H04M1/23 , H01H2221/016 , H01H2221/044
摘要： A communication terminal including a housing having elastic key buttons integrally coupled thereto is provided. The housing is configured to define an external appearance of the communication terminal. Each of the key buttons may have one end thereof integrally coupled to the housing and a free end at an opposite end thereof. A plurality of key-input switches may be respectively positioned beneath each key button. Each of the key-input switches may detect a corresponding key-input when the free end of the key button is brought into contact with the key-input switch.
摘要翻译：提供一种通信终端，其包括具有与其一体耦合的弹性键按钮的壳体。壳体被配置为限定通信终端的外观。每个按键可以将其一端整体地联接到外壳上，在其相对端具有自由端。多个按键输入开关可以分别位于每个键按钮的下方。当键按钮的自由端与键输入开关接触时，每个键输入开关可以检测相应的键输入。

47. 发明申请

US20090170250A1 TRANSISTOR OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件的晶体管及其制造方法
公开(公告)号：US20090170250A1
公开(公告)日：2009-07-02
申请号：US12396614
申请日：2009-03-03
申请人： Jae Kyoung MUN , Jong Won LIM , Woo Jin CHANG , Hong Gu JI , Ho Kyun AHN , Hae Cheon KIM
发明人： Jae Kyoung MUN , Jong Won LIM , Woo Jin CHANG , Hong Gu JI , Ho Kyun AHN , Hae Cheon KIM
IPC分类号： H01L21/338
CPC分类号： H01L29/66462 , H01L29/7785
摘要： Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased. Also, the maximum voltage limit applied to the transistor is increased due to increases in gate turn-on voltage and threshold voltage and a reduction in parallel conduction element. As a result, the power handling capability of the transistor can be improved, thus improving a high-power low-distortion characteristic and an isolation characteristic.
摘要翻译：提供半导体器件的晶体管及其制造方法。晶体管包括：设置在半绝缘衬底上并具有缓冲层的外延衬底，第一Si平面掺杂层，第一导电层，第二Si平面掺杂层和第二导电层，所述第二Si平面掺杂层具有与所述第一Si平面掺杂层的掺杂浓度不同的掺杂浓度; 源极电极和漏电极，其扩散到所述第一Si平面掺杂层中至预定深度并且设置在所述第二导电层的两侧以形成欧姆接触; 以及设置在所述源极和漏极之间的所述第二导电层上并与所述第二导电层接触的栅电极。在这种结构中，可以提高晶体管的隔离和开关速度。此外，施加到晶体管的最大电压限制由于栅极导通电压和阈值电压的增加以及并联导通元件的减小而增加。结果，可以提高晶体管的功率处理能力，从而提高高功率低失真特性和隔离特性。

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