专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US07790525B2 Method of achieving dense-pitch interconnect patterning in integrated circuits 有权
标题翻译：在集成电路中实现密集间距互连图案化的方法
公开(公告)号：US07790525B2
公开(公告)日：2010-09-07
申请号：US11874501
申请日：2007-10-18
申请人： Steven Lee Prins , James Walter Blatchford
发明人： Steven Lee Prins , James Walter Blatchford
IPC分类号： H01L21/00 , H01L21/84 , H01L21/8234
CPC分类号： G03F7/70091
摘要： Components in integrated circuits (ICs) are fabricated as small as possible to minimize sizes of the ICs and thus reduce manufacturing costs per IC. Metal interconnect lines are formed on minimum pitches possible using available photolithographic printers. Minimum pitches possible for contacts and vias are larger than minimum pitches possible for metal interconnect lines, thus preventing dense rectilinear grid configurations for contacts and vias. The instant invention is an integrated circuit, and a method of fabricating an integrated circuit, wherein metal interconnect lines are formed on a minimum pitch possible using a photolithographic printer. Contacts and vias are arranged to provide connections to components and metal interconnect lines, as required by the integrated circuit, in configurations that are compatible with the minimum pitch for contacts and vias, including semi-dense arrays.
摘要翻译：集成电路（IC）中的器件制造尽可能小，以最小化IC的尺寸，从而降低每个IC的制造成本。以可用的光刻打印机可能的最小间距形成金属互连线。触点和通孔可能的最小间距大于金属互连线可能的最小间距，从而防止用于触点和通孔的致密直线格栅配置。本发明是一种集成电路和一种制造集成电路的方法，其中使用光刻打印机以尽可能小的间距形成金属互连线。触点和通孔被布置成提供与集成电路所要求的组件和金属互连线的连接，在与包括半致密阵列的接触和通孔的最小间距兼容的配置中。

42. 发明授权

US07774739B2 Methods for adjusting shifter width of an alternating phase shifter having variable width 有权
标题翻译：用于调整具有可变宽度的交替移相器的移位器宽度的方法
公开(公告)号：US07774739B2
公开(公告)日：2010-08-10
申请号：US11565215
申请日：2006-11-30
申请人： James Walter Blatchford , Carl Albert Vickery, III
发明人： James Walter Blatchford , Carl Albert Vickery, III
IPC分类号： G06F17/50
CPC分类号： G03F1/30
摘要： In accordance with an embodiment of the invention, there is a method of designing a lithography mask. The method can comprise determining a maximum width of a shifter, wherein the maximum width corresponds to a width of a shifter for a first set of features and determining whether the shifter having the maximum width can be placed in a shifter space for a second set of features. The method can also comprise incrementally decreasing the width of the shifter to be placed into the shifter space for the second set of features when the shifter having the maximum width cannot be placed in the shifter space for a feature in the second set of features until an acceptable shifter width can be determined or until the shifter width is reduced to a predetermined minimum shifter width.
摘要翻译：根据本发明的实施例，存在设计光刻掩模的方法。该方法可以包括确定移位器的最大宽度，其中最大宽度对应于用于第一组特征的移位器的宽度，并且确定具有最大宽度的移位器是否可以被放置在第二组的移位器空间中特征。当具有最大宽度的移位器不能被放置在用于第二组特征中的特征的移位器空间中时，该方法还可以包括递增地减小要放置到用于第二组特征的移位器空间中的移位器的宽度，可以确定可接受的移位器宽度，或者直到移位器宽度减小到预定的最小移位器宽度。

43. 发明申请

US20100167513A1 DUAL ALIGNMENT STRATEGY FOR OPTIMIZING CONTACT LAYER ALIGNMENT 有权
标题翻译：用于优化联系层对齐的双对齐策略
公开(公告)号：US20100167513A1
公开(公告)日：2010-07-01
申请号：US12635906
申请日：2009-12-11
申请人： James Walter Blatchford
发明人： James Walter Blatchford
IPC分类号： H01L21/768
CPC分类号： G03F9/7046 , G03F7/70633 , G03F9/7003 , H01L27/0207 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116
摘要： An improved method for optimizing layer registration during lithography in the fabrication of a semiconductor device is disclosed. In one example, the method comprises optimizing contact layer registration of an SRAM device having a plurality of transistors having active and gate region features extending generally along a channel length (X) direction and a channel width (Y) direction, respectively. The method comprises aligning a contact layer to a gate layer in the channel length direction (X), using gate layer overlay marks to control the alignment of the contact layer in the channel length direction (X) of the semiconductor device. The method further includes aligning the contact layer to an active layer in the channel width direction (Y), using active layer overlay marks to control the alignment of the contact layer in the channel width direction (Y) of the semiconductor device.
摘要翻译：公开了一种用于在制造半导体器件的光刻期间优化层配准的改进方法。在一个示例中，该方法包括优化具有多个晶体管的SRAM器件的接触层配准，所述多个晶体管分别具有通常沿着沟道长度（X）方向和沟道宽度（Y）方向延伸的有源栅极区域特征。该方法包括使用栅极层覆盖标记将沟道长度方向（X）上的接触层与栅极层对准，以控制半导体器件的沟道长度方向（X）上接触层的对准。该方法还包括使用有源层覆盖标记将接触层与沟道宽度方向（Y）上的有源层对准，以控制接触层在半导体器件的沟道宽度方向（Y）上的对准。

44. 发明授权

US07745067B2 Method for performing place-and-route of contacts and vias in technologies with forbidden pitch requirements 有权
标题翻译：在具有禁止音高要求的技术中进行接触和通孔的放置和路径的方法
公开(公告)号：US07745067B2
公开(公告)日：2010-06-29
申请号：US11191078
申请日：2005-07-28
申请人： James Walter Blatchford , Scott William Jessen
发明人： James Walter Blatchford , Scott William Jessen
IPC分类号： G03F1/00
CPC分类号： G06F17/5068 , G03F1/36
摘要： Provide is a method of making a mask layout, an integrated circuit device made by a method, a computer readable medium, and a mask for forming contact holes. The method can comprise patterning a first feature along a first axis, determining a first set of areas adjacent to the first feature, wherein each of the areas in the first set of areas is within a first angle away from the first axis, and wherein each of the areas in the first set of areas is within a first distance away from the first feature, and patterning a second feature in at least one of the first set of areas so as to form a mask layout, wherein each of the first feature and the second feature are one of a virtual feature and a real feature.
摘要翻译：提供是制作掩模布局的方法，由方法制成的集成电路器件，计算机可读介质和用于形成接触孔的掩模。该方法可以包括沿着第一轴图案化第一特征，确定与第一特征相邻的第一组区域，其中第一组区域中的每个区域处于远离第一轴线的第一角度内，并且其中每个区域所述第一组区域中的区域在距离所述第一特征的第一距离内，并且在所述第一组区域中的至少一个中构图第二特征以形成掩模布局，其中所述第一特征和第二个特征是虚拟特征和真实特征之一。

45. 发明申请

US20080166889A1 EDA METHODOLOGY FOR EXTENDING GHOST FEATURE BEYOND NOTCHED ACTIVE TO IMPROVE ADJACENT GATE CD CONTROL USING A TWO-PRINT-TWO-ETCH APPROACH 有权
标题翻译： EDA方法用于扩展GHOST特征超过有效提高相邻门控CD使用双打印两种方法
公开(公告)号：US20080166889A1
公开(公告)日：2008-07-10
申请号：US11621605
申请日：2007-01-10
申请人： Benjamen Michael Rathsack , James Walter Blatchford
发明人： Benjamen Michael Rathsack , James Walter Blatchford
IPC分类号： H01L21/00 , G03F1/00
CPC分类号： H01L21/32139 , G03F1/36 , G03F1/70
摘要： In accordance with various embodiments, semiconductor devices and methods of forming semiconductor devices having non-rectangular active regions are provided. An exemplary method includes using a first mask to form a plurality of first features over a non-rectangular shaped active region and at least one ghost feature, wherein the plurality of first features extend beyond an edge of the non-rectangular shaped active region. The method further includes using a second mask to remove a portion of the plurality of first features extending beyond the edge of the non-rectangular shaped active region and the at least one ghost feature.
摘要翻译：根据各种实施例，提供了形成具有非矩形有源区域的半导体器件的半导体器件和方法。示例性方法包括使用第一掩模在非矩形形状的有源区域和至少一个重影特征上形成多个第一特征，其中多个第一特征延伸超过非矩形形状的有源区域的边缘。该方法还包括使用第二掩模去除延伸超过非矩形有源区域和至少一个重影特征的边缘的多个第一特征的一部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式