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41. 发明授权

US08917544B2 Phase change memory device, operation method thereof, and data storage device having the same 有权
标题翻译：相变存储器件，其操作方法和具有该相变存储器件的数据存储器件
公开(公告)号：US08917544B2
公开(公告)日：2014-12-23
申请号：US13591435
申请日：2012-08-22
申请人： Sun Hyuck Yon , Dong Keun Kim
发明人： Sun Hyuck Yon , Dong Keun Kim
IPC分类号： G11C11/21
CPC分类号： G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0057 , G11C2013/0076 , G11C2013/0092
摘要： A phase change memory device includes: a memory cell arranged at a region where a word line and a bit line cross each other; and a control logic including: a program control logic configured to control a program operation of the memory cell; a read control logic configured to control a read operation of the memory cell; and an operation complete signal transfer unit configured to adjust a transfer time point of an operation complete signal transferred between the program control logic and the read control logic.
摘要翻译：相变存储器件包括：布置在字线和位线彼此交叉的区域处的存储单元; 以及控制逻辑，包括：程序控制逻辑，被配置为控制所述存储器单元的编程操作; 读控制逻辑，被配置为控制所述存储单元的读操作; 以及操作完成信号传送单元，被配置为调整在程序控制逻辑和读取控制逻辑之间传送的操作完成信号的传送时间点。

42. 发明申请

US20140289595A1 METHOD AND SYSTEM OF PERFORMING ELECTRONIC APPROVAL PROCESSES AND COMPUTER-READABLE STORAGE MEDIUM STORING ELECTRONIC APPROVAL PROGRAM 审中-公开
标题翻译：执行电子审批程序和计算机可读存储介质存储电子认证程序的方法和系统
公开(公告)号：US20140289595A1
公开(公告)日：2014-09-25
申请号：US14222220
申请日：2014-03-21
申请人： Young-Woo PARK , Dong-Keun KIM , Dong-Min JU
发明人： Young-Woo PARK , Dong-Keun KIM , Dong-Min JU
IPC分类号： G06F17/24
CPC分类号： G06F17/241 , G06F17/242 , G06F17/248 , G06Q30/018
摘要： A letter approval item including an approval document is created in an approval requester's PC and the approval document includes a signable region. An approval is requested by transmitting the letter approval item to a database server. A mobile-based approval item including the letter approval item is provided to a web/application server and then to an approver's mobile device when the approver's mobile device requests. The approval of the letter approval item is performed in the approver's mobile device in response to a direct signature of an approver. A signature image is created in the approver's mobile device by the direct signature of the approver. The signature image is transmitted to the web/application server and a final approval document is generated in the web/application server by inserting the signature image in the signable region of the approval document.
摘要翻译：在批准申请人的PC中创建包括批准文件的信件批准项目，并且批准文件包括可签署的区域。通过将信函批准项目发送到数据库服务器来请求批准。当批准者的移动设备请求时，将包含信件批准项目的基于移动的批准项目提供给网络/应用服务器，然后提供给批准者的移动设备。信件批准项目的批准是在审批人的移动设备中进行的，以响应审批人的直接签名。通过审批者的直接签名在批准人的移动设备中创建签名图像。签名图像被发送到web /应用服务器，并且通过将签名图像插入到批准文档的可签署区域中，在web /应用服务器中生成最终批准文档。

43. 发明申请

US20140286080A1 RESISTANCE CHANGE MEMORY 有权
标题翻译：电阻变化记忆
公开(公告)号：US20140286080A1
公开(公告)日：2014-09-25
申请号：US14018011
申请日：2013-09-04
申请人： Masahiro TAKAHASHI , Dong Keun KIM , Hyuck Sang YIM
发明人： Masahiro TAKAHASHI , Dong Keun KIM , Hyuck Sang YIM
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C11/1659 , G11C11/1673 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C2013/0054
摘要： According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.
摘要翻译：根据一个实施例，电阻变化存储器包括以下配置。第一反相器包括第一输入端和第一输出端以及第一和第二电压端。第二反相器包括第二输入端和第二输出端以及第三和第四电压端。第二输入端子连接到第一输出端子。第二输出端子连接到第一输入端子。第一和第二晶体管分别连接到第一和第二输出端子。第三和第四晶体管分别连接到第一和第三电压端子。第五晶体管连接在第一电压端和第一存储单元之间。第六晶体管连接到第三电压端子。在关闭第五和第六晶体管之后，控制器接通第一和第二晶体管。

44. 发明授权

US08625362B2 Data sensing device non-volatile memory 有权
标题翻译：数据传感器非易失性存储器
公开(公告)号：US08625362B2
公开(公告)日：2014-01-07
申请号：US12980257
申请日：2010-12-28
申请人： Jung Hyuk Yoon , Dong Keun Kim
发明人： Jung Hyuk Yoon , Dong Keun Kim
IPC分类号： G11C7/10
CPC分类号： G11C13/0004 , G11C13/00 , G11C13/004 , G11C13/0061 , G11C29/026 , G11C2013/0045 , G11C2013/0057
摘要： A non-volatile memory device for measuring a read current of a unit cell is provided. The non-volatile memory device includes a unit cell configured to read or write data, a column switching unit configured to select the unit cell in response to a column selection signal, a sense amplifier controlled by a sense-amplifier enable signal, configured to sense and amplify data that is received from the unit cell through the column switching unit, a first latch unit configured to latch the sense-amplifier enable signal for a predetermined time when a test code signal received from an external part is activated, a column controller configured to output a latch control signal in response to a combination of a column switch-off signal and a column control signal, and a second latch unit configured to control whether or not the column selection signal is latched in response to an activation state of the latch control signal.
摘要翻译：提供了用于测量单元的读取电流的非易失性存储器件。非易失性存储器件包括被配置为读取或写入数据的单位单元，列切换单元，被配置为响应于列选择信号选择单位单元，由读出放大器使能信号控制的读出放大器被配置为感测并且通过列切换单元放大从单元单元接收的数据;第一锁存单元，被配置为当从外部部分接收的测试代码信号被激活时将读出放大器使能信号锁存预定时间;列控制器配置响应于列关闭信号和列控制信号的组合而输出锁存控制信号，以及第二锁存单元，被配置为响应于锁存器的激活状态来控制是否锁存列选择信号控制信号。

45. 发明授权

US08576619B2 Phase change random access memory apparatus performing a firing operation 有权
标题翻译：执行点火操作的相变随机存取存储装置
公开(公告)号：US08576619B2
公开(公告)日：2013-11-05
申请号：US13219629
申请日：2011-08-27
申请人： Jung Hyuk Yoon , Dong Keun Kim
发明人： Jung Hyuk Yoon , Dong Keun Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/00 , G11C13/0026 , G11C13/0069 , G11C29/50 , G11C2013/0083 , G11C2013/0092 , G11C2029/5002
摘要： A phase change random access memory (PCRAM) apparatus includes: a memory cell array including a plurality of phase change memory cells; and a firing control unit configured to provide a firing voltage for firing the plurality of phase change memory cells to a global bit line in response to an enable signal based on a test mode signal.
摘要翻译：相变随机存取存储器（PCRAM）装置包括：包括多个相变存储单元的存储单元阵列; 以及点火控制单元，其被配置为响应于基于测试模式信号的使能信号，将多个相变存储单元的点火电压提供给全局位线。

46. 发明授权

US08559256B2 Non-volatile memory device and sensing method thereof 有权
标题翻译：非易失性存储器件及其感测方法
公开(公告)号：US08559256B2
公开(公告)日：2013-10-15
申请号：US13212369
申请日：2011-08-18
申请人： Dong Keun Kim
发明人： Dong Keun Kim
IPC分类号： G11C7/00
CPC分类号： G11C11/5607 , G11C11/5642 , G11C11/5657 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C2013/0054
摘要： A non-volatile memory device and a sensing method thereof are disclosed, which can sense multi-level data using resistance variation. The non-volatile memory device includes a cell array and a sensing unit. The cell array includes a plurality of unit cells where data is read out or written. The sensing unit compares a sensing voltage corresponding to data stored in the unit cell with a reference voltage, amplifies/outputs the compared result, measures a difference in discharge time where the sensing voltage is discharged in response to a resistance value of the unit cell during an activation period of a sensing enable signal after a bit line is precharged, and senses the data in response to the measured result.
摘要翻译：公开了一种非易失性存储器件及其感测方法，其可以使用电阻变化感测多电平数据。非易失性存储器件包括单元阵列和感测单元。单元阵列包括读出或写入数据的多个单位单元。感测单元将对应于存储在单位单元中的数据的感测电压与参考电压进行比较，放大/输出比较结果，测量响应于单位电池电阻值的感测电压放电的放电时间差在位线被预充电之后的感测使能信号的激活周期，并且响应于测量结果感测数据。

47. 发明授权

US08472241B2 Phase change random access memory device 有权
标题翻译：相变随机存取存储器件
公开(公告)号：US08472241B2
公开(公告)日：2013-06-25
申请号：US13217362
申请日：2011-08-25
申请人： Dong Keun Kim
发明人： Dong Keun Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C7/08 , G11C13/004 , G11C2013/0054
摘要： A phase change random access memory device includes: a sense amplifier driving unit configured to compare an input voltage applied through an input signal line with a reference voltage and amplify an output signal in response to the comparison result; an input unit configured to receive an input signal from the input signal line and transmit the received signal to the sense amplifier driving unit; and a coupling prevention unit including a plurality of MOS transistors sharing a bulk bias, coupled between the sense amplifier driving unit and the input unit, and configured to control a sensing margin in response to a level of the input signal.
摘要翻译：相变随机存取存储器件包括：读出放大器驱动单元，被配置为将通过输入信号线施加的输入电压与参考电压进行比较，并响应于比较结果放大输出信号; 输入单元，被配置为从所述输入信号线接收输入信号，并将所接收的信号发送到所述读出放大器驱动单元; 以及耦合防止单元，其包括共享体偏置的多个MOS晶体管，耦合在所述读出放大器驱动单元和所述输入单元之间，并且被配置为响应于所述输入信号的电平来控制感测余量。

48. 发明授权

US08441845B2 Semiconductor memory device and control method thereof 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08441845B2
公开(公告)日：2013-05-14
申请号：US12827901
申请日：2010-06-30
申请人： Ho Seok Em , Dong Keun Kim
发明人： Ho Seok Em , Dong Keun Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C7/1048 , G11C7/12 , G11C8/14 , G11C13/0004 , G11C13/0026 , G11C13/02
摘要： A semiconductor memory device substantially prevents a faulty operation from being generated in a read operation, and increases the operation reliability. The semiconductor memory device includes a cell array configured to include a memory element having a different resistance value in response to data, a sense-amp configured to sense and amplify the data, a global bit line configured to couple the sense-amp to a cell array, and a discharge unit configured to discharge the global bit line prior to execution of a read operation.
摘要翻译：半导体存储器件基本上防止在读取操作中产生故障操作，并且增加了操作可靠性。该半导体存储器件包括一个单元阵列，其被配置为包括响应于数据具有不同电阻值的存储元件，被配置为感测和放大数据的感测放大器，被配置为将感测放大器耦合到单元的全局位线阵列和放电单元，其被配置为在执行读取操作之前对全局位线进行放电。

49. 发明授权

US08385111B2 Semiconductor memory apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US08385111B2
公开(公告)日：2013-02-26
申请号：US12844712
申请日：2010-07-27
申请人： Dong Keun Kim
发明人： Dong Keun Kim
IPC分类号： G11C11/00
CPC分类号： G11C7/18 , G11C13/0004 , G11C13/0023
摘要： A semiconductor memory apparatus includes a plurality of unit cell arrays having a plurality of word lines which are disposed in a row direction and a plurality of global bit lines which are disposed in a column direction; a row decoder configured to activate at least two word lines among the plurality of word lines in response to a row address which designates one word line; a global column switch block configured to select two different global bit lines among the plurality of global bit lines in response to column control signals; and a column decoder configured to generate the column control signals in response to a column address.
摘要翻译：一种半导体存储装置，具有：多个单元阵列，具有排列成行方向的多个字线和沿列方向配置的多个全局位线; 行解码器，其被配置为响应于指定一个字线的行地址来激活所述多个字线中的至少两个字线; 全局列切换块，被配置为响应于列控制信号选择多个全局位线中的两个不同的全局位线; 以及列解码器，被配置为响应于列地址而生成列控制信号。

50. 发明授权

US08310874B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US08310874B2
公开(公告)日：2012-11-13
申请号：US12962297
申请日：2010-12-07
申请人： Jung Hyuk Yoon , Dong Keun Kim
发明人： Jung Hyuk Yoon , Dong Keun Kim
IPC分类号： G11C16/06
CPC分类号： G11C13/0004 , G11C8/12 , G11C13/0026
摘要： A non-volatile memory device includes a cell array configured to read or write data, a local column switch configured to selectively connect a bit line of the cell array to a global bit line in response to a column selection signal, a global column switch configured to selectively connect the global bit line to a sense-amp in response to an enable signal, and a switching unit configured to selectively connect or sever a current path of the global column switch in response to a control signal corresponding to a bank active operation.
摘要翻译：非易失性存储器件包括被配置为读取或写入数据的单元阵列，配置为响应于列选择信号选择性地将单元阵列的位线连接到全局位线的本地列开关，配置的全局列开关以响应于使能信号选择性地将全局位线连接到感测放大器;以及切换单元，被配置为响应于对应于存储体激活操作的控制信号选择性地连接或切断全局列开关的当前路径。

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