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41. 发明申请

US20100214843A1 NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME 有权
标题翻译：非易失性存储器件和具有该存储器件的存储器系统
公开(公告)号：US20100214843A1
公开(公告)日：2010-08-26
申请号：US12639119
申请日：2009-12-16
申请人： Soo-Han Kim , Dae Han Kim
发明人： Soo-Han Kim , Dae Han Kim
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/26
摘要： A non-volatile memory device including a cell array having memory cells arranged at intersections of word lines and bit lines; an address decoder configured to select one of the word lines in response to an address; a write circuit configured to write program data in memory cells connected with the selected word line; and a control circuit configured to control the address decoder and the write circuit such that a plurality of band program (write) operations are sequentially executed during a write operation, wherein the control circuit is further configured to select each band write operation the optimal write condition of the next band write operation. A plurality of available write conditions are stored as trim information in a plurality of registers. The control circuit selects the register storing information for performing programming under the optimal write condition.
摘要翻译：一种非易失性存储器件，包括具有布置在字线和位线的交点处的存储单元的单元阵列; 地址解码器，被配置为响应于地址选择一条字线; 写入电路，被配置为将程序数据写入与所选择的字线连接的存储器单元中; 以及控制电路，被配置为控制地址解码器和写入电路，使得在写入操作期间顺序地执行多个频带程序（写入）操作，其中所述控制电路还被配置为选择每个频带写入操作的最佳写入条件的下一个频带写操作。多个可用写入条件作为修剪信息存储在多个寄存器中。控制电路选择用于在最佳写入条件下进行编程的寄存器存储信息。

42. 发明授权

US07710788B2 Flash memory device and method of testing a flash memory device 失效
标题翻译：闪存设备和测试闪存设备的方法
公开(公告)号：US07710788B2
公开(公告)日：2010-05-04
申请号：US11923875
申请日：2007-10-25
申请人： Hong-Soo Jeon , Dae-Han Kim
发明人： Hong-Soo Jeon , Dae-Han Kim
IPC分类号： G11C11/03
CPC分类号： G11C16/30 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A flash memory device includes a flash fuse cell array, a trim code processing unit, a flash memory array, and a regulator. The fuse cell array, which includes multiple nonvolatile fuse cells, is configured to store a first trim code. The trim code processor is configured to generate a second trim code based on the first trim code provided by the fuse cell array and a voltage control code. The flash memory array includes multiple flash memory cells. The regulator is configured to generate a high voltage in response to the second trim code and to provide the high voltage to the flash memory array. The high voltage varies according to erase, program and read operations of the flash memory cells.
摘要翻译：闪存器件包括闪存熔丝单元阵列，修剪代码处理单元，闪存阵列和调节器。包括多个非易失性熔丝单元的熔丝单元阵列被配置为存储第一微调代码。修剪码处理器被配置为基于由熔丝单元阵列提供的第一修剪码和电压控制码产生第二修剪码。闪存阵列包括多个闪存单元。调节器被配置为响应于第二修剪代码产生高电压并且向闪存阵列提供高电压。高电压根据闪存单元的擦除，编程和读取操作而变化。

43. 发明申请

US20080170450A1 METHOD FOR TESTING INTERNAL HIGH VOLTAGE IN NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND RELATED VOLTAGE OUTPUT CIRCUIT 失效
标题翻译：在非易失性半导体存储器件和相关电压输出电路中测试内部高电压的方法
公开(公告)号：US20080170450A1
公开(公告)日：2008-07-17
申请号：US11957808
申请日：2007-12-17
申请人： Chae-Hoon KIM , Dae-Han KIM
发明人： Chae-Hoon KIM , Dae-Han KIM
IPC分类号： G11C29/50 , G11C16/06
CPC分类号： G11C16/30 , G11C5/145 , G11C16/04 , G11C27/024 , G11C29/02 , G11C29/021
摘要： In a voltage output circuit of a nonvolatile semiconductor memory device, a high voltage generator generates an internal high voltage, a sampling signal generator generates a sampling signal, and a sample and old circuit samples and holds the internal high voltage in accordance with the sampling signal.
摘要翻译：在非易失性半导体存储器件的电压输出电路中，高电压发生器产生内部高电压，采样信号发生器产生采样信号，采样和旧电路采样并根据采样信号保持内部高电压。

44. 发明授权

US07372747B2 Flash memory device and voltage generating circuit for the same 有权
标题翻译：闪存器件和电压发生电路相同
公开(公告)号：US07372747B2
公开(公告)日：2008-05-13
申请号：US11482447
申请日：2006-07-07
申请人： Sang-Wan Nam , Dae-Han Kim
发明人： Sang-Wan Nam , Dae-Han Kim
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C16/08 , G11C16/12
摘要： A flash memory device and a voltage generating circuit for the same. The flash memory includes a memory cell array configured with a plurality of memory cells, a voltage generating circuit for generating a plurality of constant voltages to be applied to the memory cell array, and a selection circuit for selecting one constant voltage among the plurality of the constant voltages and applying the selected one constant voltage to the memory cell array. The voltage generating circuit discharges a leakage current input by the selection circuit through a voltage division path, which generates the constant voltages.
摘要翻译：一种闪存器件及其电压产生电路。闪存包括配置有多个存储单元的存储单元阵列，用于产生施加到存储单元阵列的多个恒定电压的电压产生电路，以及用于选择多个存储单元中的一个恒定电压的选择电路将所选择的一个恒定电压施加到存储单元阵列。电压产生电路通过分压路径对由选择电路输入的漏电流进行放电，产生恒定电压。

45. 发明申请

US20070201277A1 NOR flash memory device with a serial sensing operation and method of sensing data bits in a NOR flash memory device 审中-公开
公开(公告)号：US20070201277A1
公开(公告)日：2007-08-30
申请号：US11789624
申请日：2007-04-25
申请人： Sang-Wan Nam , Young-Ho Lim , Dae-Han Kim
发明人： Sang-Wan Nam , Young-Ho Lim , Dae-Han Kim
IPC分类号： G11C16/04 , G11C16/06 , G11C11/34
CPC分类号： G11C16/26
摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

46. 发明申请

US20060215449A1 NOR flash memory device with a serial sensing operation and method of sensing data bits in a NOR flash memory device 失效
标题翻译：具有串行感测操作的NOR闪存器件和用于检测NOR闪存器件中的数据位的方法
公开(公告)号：US20060215449A1
公开(公告)日：2006-09-28
申请号：US11263716
申请日：2005-11-01
申请人： Sang-Wan Nam , Young-Ho Lim , Dae-Han Kim
发明人： Sang-Wan Nam , Young-Ho Lim , Dae-Han Kim
IPC分类号： G11C16/04
CPC分类号： G11C16/26
摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.
摘要翻译：在具有串行感测操作的NOR闪存器件中，以及在NOR闪存器件中检测数据位的方法，该器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑电路。感测放大电路串行地检测存储在多电平单元中的多个数据位。提供数据缓冲器以缓冲由读出放大器检测到的数据位。数据锁存电路一次存储数据缓冲器的输出值。控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。

47. 发明授权

US06724245B2 Boosting circuit 有权
标题翻译：升压电路
公开(公告)号：US06724245B2
公开(公告)日：2004-04-20
申请号：US10329460
申请日：2002-12-27
申请人： Yi Jin Kwon , Dae Han Kim
发明人： Yi Jin Kwon , Dae Han Kim
IPC分类号： H03K508
CPC分类号： G11C16/08 , G11C8/08
摘要： The present invention relates to a boosting circuit. A boosting voltage (VBOOT) is dropped to a given voltage level through a pre-select clamp circuit and the boosting voltage (VBOOT) is again dropped through a clamp circuit, depending on the power supply voltage, so that a final target word line voltage is generated. Accordingly, a read access time is rapid upon a read operation, the current consumption is minimized and a stabilized word line voltage can be generated.
摘要翻译：本发明涉及升压电路。升压电压（VBOOT）通过预选钳位电路下降到给定电压电平，并且根据电源电压，升压电压（VBOOT）再次通过钳位电路下降，使得最终目标字线电压被生成。因此，在读取操作时读取访问时间很快，电流消耗最小化并且可以产生稳定的字线电压。

48. 发明授权

US06445616B2 Nonvolatile memory sensing circuit and techniques thereof 有权
标题翻译：非易失性存储器感测电路及其技术
公开(公告)号：US06445616B2
公开(公告)日：2002-09-03
申请号：US09901898
申请日：2001-07-11
申请人： Dae-Han Kim
发明人： Dae-Han Kim
IPC分类号： G11C1606
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5642 , G11C2211/5634
摘要： The nonvolatile memory sensing circuit includes a main cell part and at least one reference cell part, including a main cell array having a plurality of main cells to which a word line driving signal is applied respectively, a plurality of main cell switches receiving a plurality of main cell selection signals YG0 to YGn which switch to select one of the main cells wherein the main cell switches are connected to the main cell array in series, a main cell bit line voltage controller maintaining drain voltage to a fixed level by receiving program bias voltage PRBIAS, a main cell path transistor connected between an output of the main cell bit line voltage controller and internal power supply voltage wherein the main cell path transistor outputting a state of the main cell, and at least one sense amplifier producing a comparison output SAOUT by receiving at least one reference voltage RDREF and an output SENSE of the main cell path transistor, and wherein the reference cell part further comprises a program reference cell part and read reference cell part which share a voltage controlling means regulating drain or source voltage to a predetermined level and wherein the reference cell part produces reference voltage RDREF of fixed level.
摘要翻译：非易失性存储器感测电路包括主单元部分和至少一个参考单元部分，包括分别施加有字线驱动信号的多个主单元的主单元阵列，多个主单元开关，其接收多个主单元选择信号YG0至YGn，其切换以选择其中主单元开关串联连接到主单元阵列的主单元之一;主单元位线电压控制器，通过接收编程偏置电压将漏极电压维持在固定电平 PRBIAS，连接在主单元位线电压控制器的输出和输出主单元的状态的主单元路径晶体管的内部电源电压之间的主单元路径晶体管，以及至少一个读出放大器，其通过以下方式产生比较输出SAOUT：接收主单元路径晶体管的至少一个参考电压RDREF和输出SENSE，并且其中参考单元部分进一步c 具有节目参考单元部分和读取参考单元部分，其共享将电源电压调节到预定电平的电压控制装置，并且其中参考单元部分产生固定电平的参考电压RDREF。

49. 发明授权

US6087890A Redundancy fuse read circuit 有权
标题翻译：冗余保险丝读取电路
公开(公告)号：US6087890A
公开(公告)日：2000-07-11
申请号：US197468
申请日：1998-11-23
申请人： Dae-Han Kim
发明人： Dae-Han Kim
IPC分类号： H01H85/46 , G11C29/00 , H03K19/003
CPC分类号： G11C29/787
摘要： A redundancy fuse read circuit includes an external source voltage detector for detecting a voltage level of an external source voltage and generating a HIGH enable detection signal, a fuse information storage unit for generating fuse information by capacitive coupling in accordance with the HIGH enable detection signal and for sensing the fuse information, and a comparator for comparing an output signal of the fuse information storage unit and one of an internal and external address signals.
摘要翻译：冗余熔丝读取电路包括用于检测外部电源电压的电压电平并产生高使能检测信号的外部电源电压检测器，用于根据高使能检测信号通过电容耦合产生熔丝信息的熔丝信息存储单元，以及用于感测熔丝信息;以及比较器，用于比较熔丝信息存储单元的输出信号和内部和外部地址信号之一。

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