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41. 发明专利

JP4467721B2 Test method using the contactor and contactor 有权
公开(公告)号：JP4467721B2
公开(公告)日：2010-05-26
申请号：JP2000191405
申请日：2000-06-26
申请人：富士通マイクロエレクトロニクス株式会社
发明人：茂幸丸山 , 直行渡辺 , 映矢野 , 隆文端谷 , 一郎緑川 , 進貴田
IPC分类号： G01R31/26 , G01R1/04 , G01R1/067 , G01R1/073 , H01L21/66 , H01L23/498
CPC分类号： G01R1/06733 , G01R1/0483 , G01R1/06711 , G01R1/06755 , G01R1/07314 , H01L23/49827 , H01L2924/0002 , H01L2924/00

42. 发明专利

JP4467162B2 A method of manufacturing a semiconductor device 有权
公开(公告)号：JP4467162B2
公开(公告)日：2010-05-26
申请号：JP2000277416
申请日：2000-09-13
申请人：富士通マイクロエレクトロニクス株式会社
发明人：雅彦東
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/78

43. 发明专利

JP4463378B2 Non-volatile semiconductor memory device 有权
公开(公告)号：JP4463378B2
公开(公告)日：2010-05-19
申请号：JP2000133765
申请日：2000-05-02
申请人：富士通マイクロエレクトロニクス株式会社
发明人：潤弥川又
IPC分类号： G06F12/14 , G11C16/02 , G06F21/02 , G06F21/24 , G11C16/08 , G11C16/22
CPC分类号： G11C16/22 , G11C16/08

44. 发明专利

JP2010109174A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010109174A
公开(公告)日：2010-05-13
申请号：JP2008280094
申请日：2008-10-30
申请人： Fujitsu Ltd , Fujitsu Microelectronics Ltd , 富士通マイクロエレクトロニクス株式会社 , 富士通株式会社
发明人： SUZUKI TAKASHI , OZAWA KIYOSHI
IPC分类号： H01L27/08 , H01L21/76 , H01L21/8238 , H01L27/092
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, wherein an etching height is not varied by a change in an etching speed due to ion implantation to an element isolation insulating film when forming a CMOS having an STI type element isolation structure. SOLUTION: The method for manufacturing the semiconductor device includes: a step for forming an element isolation region having an STI structure on a silicon substrate 21; and a step for forming a first well and a second well by doping first impurity elements into a first element region 21A of the silicon substrate 21 by first ion implantation in a state that the first region 21A of the silicon substrate 21 and an element isolation insulating film 21IB of a second element region 21B are covered with an opened first resist pattern R21B and doping second impurity elements into the second element region 21B of the silicon substrate 21 by second ion implantation in a state that the second region 21B of the silicon substrate 21 and an element isolation insulating film 21IA of the first element region 21A are covered with an opened second resist pattern R21A. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种制造半导体器件的方法，其中当形成具有STI型CMOS的CMOS时，由于离子注入到元件隔离绝缘膜时蚀刻速度的变化不会改变蚀刻高度元件隔离结构。解决方案：制造半导体器件的方法包括：在硅衬底21上形成具有STI结构的元件隔离区的步骤; 以及通过在硅衬底21的第一区域21A和元件隔离绝缘体的状态下通过第一离子注入将第一杂质元素掺杂到硅衬底21的第一元件区域21A中而形成第一阱和第二阱的步骤第二元件区域21B的膜21IB被打开的第一抗蚀剂图案R21B覆盖，并且通过第二离子注入在硅衬底21的第二区域21B的状态下将第二杂质元素掺杂到硅衬底21的第二元件区域21B中并且第一元件区域21A的元件隔离绝缘膜21IA被打开的第二抗蚀剂图案R21A覆盖。版权所有（C）2010，JPO＆INPIT

45. 发明专利

JP2010109047A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010109047A
公开(公告)日：2010-05-13
申请号：JP2008278060
申请日：2008-10-29
申请人： Fujitsu Microelectronics Ltd , 富士通マイクロエレクトロニクス株式会社
发明人： ISHIHARA YUKIHIRO
IPC分类号： H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device allowing a transistor for a digital circuit and a transistor for an analog circuit having characteristics different from each other to be formed by a common process, and a method of manufacturing the same. SOLUTION: In this semiconductor device, a distance L1 from an end on a gate electrode 24a side of a first low-concentration diffusion layer 28N of an N-type high-withstand-voltage transistor 42N for an analog circuit to an end on a gate electrode 24a side of a second low-concentration diffusion layer 30N is set longer than a distance L3 from an end on a gate electrode 24b side of a first low-concentration diffusion layer 48N of a high-withstand-voltage transistor 52N for a digital circuit to an end on a gate electrode 24b of a second low-concentration diffusion layer 50N. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供允许用于数字电路的晶体管和具有彼此不同的特性的模拟电路的晶体管通过公共处理形成的半导体器件及其制造方法。解决方案：在该半导体器件中，从用于模拟电路的N型高耐压晶体管42N的第一低浓度扩散层28N的栅极电极24a侧的端部到端部的距离L1 在第二低浓度扩散层30N的栅电极24a侧设定为比从高耐压晶体管52N的第一低浓度扩散层48N的栅电极24b侧的端部起的距离L3长，数字电路到第二低浓度扩散层50N的栅电极24b的一端。版权所有（C）2010，JPO＆INPIT

46. 发明专利

JP2010098594A Demodulation circuit and method 审中-公开
标题翻译：解调电路和方法
公开(公告)号：JP2010098594A
公开(公告)日：2010-04-30
申请号：JP2008268806
申请日：2008-10-17
申请人： Fujitsu Microelectronics Ltd , 富士通マイクロエレクトロニクス株式会社
发明人： YOSHIDA MASAHIRO
IPC分类号： H04J11/00 , H03M13/01 , H04L1/00
摘要： PROBLEM TO BE SOLVED: To accomplish an OFDMA demodulation circuit which reduces circuit scale and power consumption.
SOLUTION: The present invention relates to a demodulation circuit wherein a plurality of burst regions are defined inside a frame defined by a symbol direction and a sub carrier direction, comprising: a symbol memory 31 for storing reception data obtained by demodulating a reception signal in the unit of a symbol; a transmission line estimation and compensation circuit 26 for performing transmission line estimation and compensation processing of the reception data stored in the symbol memory in the unit of a symbol; a buffer 32 for storing and outputting outputs of the transmission line estimation and compensation circuit in the unit of a block in error correction processing; and an error correction circuit 27 for performing error correction processing in the unit of a block on the transmission line estimation and compensation processed reception data output from the buffer.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：实现减少电路规模和功耗的OFDMA解调电路。解决方案：本发明涉及一种解调电路，其中在由符号方向和子载波方向定义的帧内部定义多个突发区域，包括：符号存储器31，用于存储通过解调接收获得的接收数据以符号为单位的信号; 用于以符号为单位对存储在符号存储器中的接收数据进行传输线估计和补偿处理的传输线路估计和补偿电路26; 缓冲器32，用于以误差校正处理为单位存储和输出传输线路估计和补偿电路的输出; 以及误差校正电路27，用于以传输线路估计的块为单位进行纠错处理，并从缓冲器输出补偿处理的接收数据。版权所有（C）2010，JPO＆INPIT

47. 发明专利

JP2010097386A Data management method 审中-公开
标题翻译：数据管理方法
公开(公告)号：JP2010097386A
公开(公告)日：2010-04-30
申请号：JP2008267288
申请日：2008-10-16
申请人： Fujitsu Microelectronics Ltd , 富士通マイクロエレクトロニクス株式会社
发明人： NAKAJIMA ISAMU
IPC分类号： G06F12/16
摘要： PROBLEM TO BE SOLVED: To correctly manage data in data management of flash memory. SOLUTION: When power supply interception occurs during program operation on the flash memory, the interrupted processing is determined, when detecting that the processing of program operation has been interrupted by interception of the power supply after restoration of power supply (step S1). The program operation is started from one processing prior to the processing determined that it is interrupted, and a memory cell of an unstable status is returned to a stable memory cell by overwriting data to the memory cell of inadequate writing (step S2). COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：正确管理闪存数据管理中的数据。解决方案：当在闪速存储器的编程操作期间发生电源截取时，当检测到在恢复供电之后通过截取电源中断编程操作的处理时，确定中断的处理（步骤S1）。程序操作从处理之前的一个处理开始确定它被中断，并且通过向存储器单元写入不足写入的数据，将不稳定状态的存储单元返回到稳定的存储单元（步骤S2）。版权所有（C）2010，JPO＆INPIT

48. 发明专利

JP4458923B2 Image processing apparatus 有权
公开(公告)号：JP4458923B2
公开(公告)日：2010-04-28
申请号：JP2004141454
申请日：2004-05-11
申请人：富士通マイクロエレクトロニクス株式会社
发明人：康洲鎌 , 宗典瀧本
IPC分类号： H04N19/102 , H04N7/24 , H04N19/00 , H04N19/134 , H04N19/136 , H04N19/156 , H04N19/159 , H04N19/196 , H04N19/37

49. 发明专利

JP4456995B2 Semiconductor memory device 有权
公开(公告)号：JP4456995B2
公开(公告)日：2010-04-28
申请号：JP2004360384
申请日：2004-12-13
申请人：富士通マイクロエレクトロニクス株式会社
发明人：秀雄穐吉
IPC分类号： G11C11/41 , G11C11/401 , G11C11/417
CPC分类号： G11C7/1048 , G11C5/063 , G11C7/10 , G11C11/413

50. 发明专利

JP2010093380A Ofdm demodulation device and ofdm demodulating method 有权
标题翻译： OFDM解调设备和OFDM解调方法
公开(公告)号：JP2010093380A
公开(公告)日：2010-04-22
申请号：JP2008258794
申请日：2008-10-03
申请人： Fujitsu Microelectronics Ltd , 富士通マイクロエレクトロニクス株式会社
发明人： HAMAMINATO MAKOTO , ADACHI NAOTO
IPC分类号： H04J11/00
摘要： PROBLEM TO BE SOLVED: To provide an OFDM (Orthogonal Frequency Division Multiplexing) demodulation device which prevents the degradation of receiving quality even when spurious components are mixed in a receiving signal.
SOLUTION: A FFT (Fast Fourier Transform) unit 23 creates a frequency domain signal by executing butterfly operation of multiple times for the OFDM receiving signal. A demodulating unit 24 demodulates the frequency domain signal created by the FFT unit 23. The FFT unit 23 carries out scaling of respective signal components based on the maximum power of signal components excluding detected spurious components for the results of the last butterfly operation when the spurious components are detected.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供即使在接收信号中混合杂散分量时也可防止接收质量下降的OFDM（正交频分复用）解调装置。解决方案：FFT（快速傅里叶变换）单元23通过对OFDM接收信号执行多次蝶形运算来产生频域信号。解调单元24解调由FFT单元23产生的频域信号。FFT单元23基于最后一个蝶形运算结果的信号分量的最大功率，除去检测到的杂散分量之后，对伪信号进行缩放检测到组件。版权所有（C）2010，JPO＆INPIT

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