专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

WO2004095522A2 DEEP N WELLS IN TRIPLE WELL STRUCTURES AND METHOD FOR FABRICATING SAME 审中-公开
标题翻译：三层结构中的深层N孔和其制造方法
公开(公告)号：WO2004095522A2
公开(公告)日：2004-11-04
申请号：PCT/US2004/001877
申请日：2004-01-24
申请人： NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTOR
发明人： KAR-ROY, Arjun , RACANELLI, Marco , ZHANG, Jinshu
IPC分类号： H01L
CPC分类号： H01L21/761 , H01L21/74 , H01L21/823878 , H01L21/823892 , H01L27/0928
摘要： A disclosed method for fabricating a structure in a semiconductor die comprises steps of implanting a deep N well in a substrate, depositing an epitaxial layer over the substrate, and forming a P well and a lateral isolation N well over the deep N well, wherein the lateral isolation N well and the P well are fabricated in the substrate and the epitaxial layer, and wherein the lateral isolation N well laterally surrounds the P well, and wherein the deep N well and the lateral isolation N well electrically isolate the P well. Implanting a deep N well can comprise steps of depositing a screen oxide layer over the substrate, forming a mask over the screen oxide layer, implanting the deep N well in the substrate, removing the mask, and removing the screen oxide layer. Depositing the epitaxial layer can comprise depositing a single crystal silicon over the substrate.
摘要翻译：一种用于在半导体管芯中制造结构的方法包括以下步骤：在衬底中注入深N阱，在衬底上沉积外延层，并在深N阱上形成P阱和横向隔离N，其中横向隔离N阱和P阱在衬底和外延层中制造，并且其中横向隔离N阱横向围绕P阱，并且其中深N阱和横向隔离N良好地电隔离P阱。植入深N阱可以包括在衬底上沉积屏幕氧化物层，在屏幕氧化物层上形成掩模，在衬底中注入深N阱，去除掩模和去除屏蔽氧化物层的步骤。沉积外延层可以包括在衬底上沉积单晶硅。

42. 发明申请

WO2004036621A2 METHOD FOR IMPROVED ALIGNMENT TOLERANCE IN A BIPOLAR TRANSISTOR AND RELATED STRUCTURE 审中-公开
标题翻译：用于改善双极晶体管中的对准公差的方法及相关结构
公开(公告)号：WO2004036621A2
公开(公告)日：2004-04-29
申请号：PCT/US2003/014567
申请日：2003-05-08
申请人： NEWPORT FAB, LLC dba JAZZ SEMICONDUCTOR
发明人： SCHUEGRAF, Klaus, F.
IPC分类号： H01L
CPC分类号： H01L29/66242
摘要： According to one exemplary embodiment, a bipolar transistor, such as a heterojunction bipolar transistor ("HBT"), comprises a base (327) having a top surface (324). The HBT further comprises a first inner spacer (317) and a second inner (318) spacer situated on the top surface of the base. The HBT further comprises a first outer spacer (327) situated adjacent to the first inner spacer (317) and a second outer spacer (328) situated adjacent to the second inner spacer (318) on the top surface (324) of the base (327). According to this exemplary embodiment, the HBT further comprises an emitter (326) situated between the first and second inner spacers (317, 318). The HBT may further comprise an intermediate oxide layer (316) situated on the first and second outer spacers (327, 328). The HBT may further comprise an amorphous layer (321) situated on said intermediate oxide layer (316). The HBT may also comprise an antireflective coating layer (322) on the amorphous layer (321).
摘要翻译：根据一个示例性实施例，诸如异质结双极晶体管（“HBT”）的双极晶体管包括具有顶表面（324）的基极（327）。 HBT还包括位于基座的顶表面上的第一内部间隔件（317）和第二内部（318）间隔件。 HBT还包括位于第一内部间隔件（317）附近的第一外部间隔件（327）和位于基部的顶部表面（324）上邻近第二内部间隔件（318）的第二外部间隔件（328） 327）。根据该示例性实施例，HBT还包括位于第一和第二内部间隔件（317,318）之间的发射器（326）。 HBT还可以包括位于第一和第二外隔离物（327,328）上的中间氧化物层（316）。 HBT还可以包括位于所述中间氧化物层（316）上的非晶层（321）。 HBT还可以包括在非晶层（321）上的抗反射涂层（322）。

43. 发明申请

WO2003067655A1 METHOD AND STRUCTURE FOR FORMING AN HBT 审中-公开
标题翻译：形成HBT的方法和结构
公开(公告)号：WO2003067655A1
公开(公告)日：2003-08-14
申请号：PCT/US2002/038146
申请日：2002-11-27
申请人： NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTOR
发明人： U'REN, Greg, D. , SCHUEGRAF, Klaus, F. , RACANELLI, Marco
IPC分类号： H01L21/8222
CPC分类号： H01L29/66242 , H01L29/1004 , H01L29/7378
摘要： According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a concentration of germanium, where the concentration of germanium decreases between first depth (420) and a second depth (422) in the base. According to this exemplary embodiment, the base of the heterojunction bipolar transistor further comprises a concentration of a diffusion suppressant of a base dopant, where the concentration of the diffusion suppressant decreases between a third depth (419) and a fourth depth (421) so as to counteract a change in band gap in the base between the first depth (420) and the second depth (422). For example, the diffusion suppressant can be carbon and the base dopant can be boron. For example, the concentration of diffusion suppressant may decrease between the third depth (419) and fourth depth (421) so as to counteract the change in band gap at approximately the second depth (422).
摘要翻译：根据一个示例性实施例，异质结双极晶体管包括具有锗浓度的基底，其中锗的浓度在基底中的第一深度（420）和第二深度（422）之间降低。根据该示例性实施例，异质结双极晶体管的基极还包括基极掺杂剂的扩散抑制剂的浓度，其中扩散抑制剂的浓度在第三深度（419）和第四深度（421）之间降低，从而以抵消第一深度（420）和第二深度（422）之间的基底中的带隙的变化。例如，扩散抑制剂可以是碳，碱性掺杂剂可以是硼。例如，扩散抑制剂的浓度可以在第三深度（419）和第四深度（421）之间减小，以抵消大致第二深度（422）处的带隙的变化。

44. 发明申请

WO2004044988A1 HIGH GAIN BIPOLAR TRANSISTOR 审中-公开
标题翻译：高增益双极晶体管
公开(公告)号：WO2004044988A1
公开(公告)日：2004-05-27
申请号：PCT/US2003/027227
申请日：2003-08-29
申请人： NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTOR
发明人： ZHENG, Jie , YE, Peihua , RACANELLI, Marco
IPC分类号： H01L27/082
CPC分类号： H01L29/0808 , H01L29/735
摘要： According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface (248). The bipolar transistor might be a lateral PNP bipolar transistor and the base may comprise, for example, N type single crystal silicon. The bipolar transistor further comprises an emitter (206) having a top surface, where the emitter is situated on top surface of the base. The emitter may comprise P+ type single crystal silicon-germanium, for example. The bipolar transistor further comprises an electron barrier layer situated directly on the top surface of the emitter. The electron barrier layer will cause an increase in the gain, or beta, of the bipolar transistor. The electron barrier layer may be a dielectric such as, for example, silicon oxide. In another embodiment, a floating N + region, instead of the electron barrier layer (244), is utilized to increase the gain of the bipolar transistor.
摘要翻译：根据一个示例性实施例，双极晶体管包括具有顶表面（248）的基座。双极晶体管可以是横向PNP双极晶体管，并且基极可以包括例如N型单晶硅。双极晶体管还包括具有顶表面的发射极（206），其中发射极位于基极的顶表面上。例如，发射极可以包括P +型单晶硅 - 锗。双极晶体管还包括直接位于发射极的顶表面上的电子势垒层。电子势垒层将引起双极晶体管的增益或β的增加。电子势垒层可以是电介质，例如氧化硅。在另一个实施例中，利用浮动N +区而不是电子势垒层（244）来增加双极晶体管的增益。

45. 发明申请

WO2006118652A2 METHOD FOR FABRICATING A MIM CAPACITOR HIGH-K DIELECTRIC FOR INCREASED CAPACITANCE DENSITY AND RELATED STRUCTURE 审中-公开
标题翻译：用于制造MIM电容器高K电介质以增加电容密度和相关结构的方法
公开(公告)号：WO2006118652A2
公开(公告)日：2006-11-09
申请号：PCT/US2006/007406
申请日：2006-03-01
申请人： NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTOR , ABDUL-RIDHA, Hadi, H. , HOWARD, David, J.
发明人： ABDUL-RIDHA, Hadi, H. , HOWARD, David, J.
IPC分类号： H01L21/20
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a high-k dielectric layer comprising AlNx (aluminum nitride) on the first interconnect layer. The method further includes depositing a layer of MIM capacitor metal on the high-k dielectric layer. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the first interconnect metal layer, the high-k dielectric layer, and the layer of MIM capacitor metal can be deposited in a PVD process chamber. The method further includes etching the high-k dielectric layer to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor.
摘要翻译：根据本发明的一个实施例，在半导体管芯中制造MIM电容器的方法包括沉积第一互连金属层的步骤。该方法还包括在第一互连层上沉积包含AlNx（氮化铝）的高k电介质层。该方法还包括在高k电介质层上沉积MIM电容器金属层。该方法还包括蚀刻MIM电容器金属层以形成MIM电容器的上电极。根据该示例性实施例，第一互连金属层，高k电介质层和MIM电容器金属层可以沉积在PVD处理室中。该方法还包括蚀刻高k电介质层以形成MIM电容器介电段并蚀刻第一互连金属层以形成MIM电容器的下电极。

46. 发明申请

WO2004107410B1 SELF-ALIGNED BIPOLAR TRANSISTOR HAVING RECESSED SPACERS AND METHOD FOR FABRICATING SAME 审中-公开
标题翻译：具有凹入空间的自对准双极晶体管及其制造方法
公开(公告)号：WO2004107410B1
公开(公告)日：2005-09-15
申请号：PCT/US2004008387
申请日：2004-03-19
申请人： NEWPORT FAB LLC D B A JAZZ SEM
发明人： KALBURGE AMOL , YIN KEVIN Q
IPC分类号： H01L21/331 , H01L29/08 , H01L29/80 , H01L21/8222 , H01L31/112
CPC分类号： H01L29/66272 , H01L29/0804 , H01L29/66242 , H01L29/66287
摘要： According to one exemplary embodiment, a bipolar transistor comprises a base (320) having a top surface (326). The bipolar transistor further comprises a first link spacer (314) and a second link spacer (316) situated on the top surface (326) of the base (320). The bipolar transistor further comprises a sacrificial post (302) situated between the first and second link spacers (314 and 316), where the first and second link spacers (314 and 316) have a height (313) that is substantially less than a height (315) of the sacrificial post (302). The bipolar transistor also comprises a conformal layer (322) situated over the sacrificial post (302) and the first and second link spacers (314 and 316). According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer (324) situated over the conformal layer (322), the first and second link spacers (314 and 316), the sacrificial post (302), and the base (320). The sacrificial planarizing layer (324) may comprise, for example, an organic material such as an organic BARC ("bottom anti-reflective coating").
摘要翻译：根据一个示例性实施例，一种双极晶体管包括具有顶表面（326）的基座（320）。双极晶体管还包括位于基座（320）的顶表面（326）上的第一连接间隔件（314）和第二连接间隔件（316）。双极晶体管进一步包括位于第一和第二链接间隔件（314和316）之间的牺牲柱（302），其中第一和第二链接间隔件（314和316）具有基本上小于高度（302）的第一部分（315）。双极晶体管还包括位于牺牲柱（302）以及第一和第二连接间隔件（314和316）上的共形层（322）。根据该示例性实施例，双极晶体管还包括位于共形层（322），第一和第二连接间隔件（314和316），牺牲柱（302）以及底座（322）上的牺牲平面化层（324） 320）。牺牲平坦化层（324）可以包括例如有机材料，诸如有机BARC（“底部抗反射涂层”）。

47. 发明申请

WO2004107445A1 METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR WITH PLANARIZING LAYER AND RELATED STRUCTURE 审中-公开
标题翻译：一种具有平面化层的自对准双极晶体管和相关结构的方法
公开(公告)号：WO2004107445A1
公开(公告)日：2004-12-09
申请号：PCT/US2004/008397
申请日：2004-03-20
申请人： NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTOR
发明人： KALBURGE, Amol , YIN, Kevin, Q.
IPC分类号： H01L27/082
CPC分类号： H01L29/66287 , H01L29/66242 , H01L29/66318
摘要： According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises first and second link spacers situated on the top surface of the base. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base between the first and second link spacers. The first and second link spacers may have a height, for example, approximately equal to or, in another embodiment, substantially less than a height of the sacrificial post. According to this exemplary embodiment, the bipolar transistor further comprises a non-sacrificial planarizing layer situated over the sacrificial post, first and second link spacers, and base. The non-sacrificial planarizing layer may comprise, for example, silicate glass. The sacrificial planarizing layer may have a height, for example, approximately equal to or, in another embodiment, greater than greater than a height of the first and second link spacers.
摘要翻译：根据一个示例性实施例，双极晶体管包括具有顶表面的基座。双极晶体管还包括位于基座的顶表面上的第一和第二连接间隔物。双极晶体管还包括位于第一和第二连接间隔物之间的基底的顶表面上的牺牲柱。第一和第二连接间隔件可以具有例如大约等于或者在另一实施例中的高度，其大大小于牺牲柱的高度。根据该示例性实施例，双极晶体管还包括位于牺牲柱，第一和第二连接间隔件以及基座之上的非牺牲平坦化层。非牺牲平坦化层可以包括例如硅酸盐玻璃。牺牲平坦化层可以具有例如大约等于或者在另一个实施例中的高度大于大于第一和第二连接间隔物的高度的高度。

48. 发明申请

WO2004107410A2 SELF-ALIGNED BIPOLAR TRANSISTOR HAVING RECESSED SPACERS AND METHOD FOR FABRICATING SAME 审中-公开
标题翻译：具有保持间隔物的自对准双极晶体管及其制造方法
公开(公告)号：WO2004107410A2
公开(公告)日：2004-12-09
申请号：PCT/US2004/008387
申请日：2004-03-19
申请人： NEWPORT FAB, LLC d.b.a. JAZZ SEMICONDUCTOR
发明人： KALBURGE, Amol , YIN, Kevin, Q.
IPC分类号： H01L
CPC分类号： H01L29/66272 , H01L29/0804 , H01L29/66242 , H01L29/66287
摘要： According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a first link spacer and a second link spacer situated on the top surface of the base. The bipolar transistor further comprises a sacrificial post situated between the first and second link spacers, where the first and second link spacers have a height that is substantially less than a height of the sacrificial post. The bipolar transistor also comprises a conformal layer situated over the sacrificial post and the first and second link spacers. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the first and second link spacers, the sacrificial post, and the base. The sacrificial planarizing layer may comprise, for example, an organic material such as an organic BARC ("bottom anti-reflective coating").
摘要翻译：根据一个示例性实施例，双极晶体管包括具有顶表面的基座。双极晶体管还包括第一连接间隔物和位于基底的顶表面上的第二连接间隔物。所述双极晶体管还包括位于所述第一和第二连接间隔件之间的牺牲柱，其中所述第一和第二连接间隔件的高度实质上小于所述牺牲柱的高度。双极晶体管还包括位于牺牲柱和第一和第二连接间隔物之上的共形层。根据该示例性实施例，双极晶体管还包括位于保形层之上的牺牲平坦化层，第一和第二连接间隔物，牺牲柱和基底。牺牲平坦化层可以包括例如有机材料，例如有机BARC（“底部抗反射涂层”）。

49. 发明申请

WO2004062083A1 BiFET VOLTAGE CONTROLLED OSCILLATOR 审中-公开
标题翻译： BiFET电压控制振荡器
公开(公告)号：WO2004062083A1
公开(公告)日：2004-07-22
申请号：PCT/US2003/029256
申请日：2003-09-17
申请人： NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTOR
发明人： MA, Pingxi , RACANELLI, Marco
IPC分类号： H03B5/12
CPC分类号： H03B5/1231 , H03B5/1215 , H03B5/1243 , H03B2200/0038
摘要： According to one exemplary embodiment, a VCO core circuit is connected across a first node and a second node. The anode of a first varactor is connected to the first node while the anode of a second varactor is connected to the second node, and the cathode of the first varactor is tied to the cathode of the second varactor. A tuning voltage is also connected to the cathode of the first varactor and the cathode of the second varactor. The inductor is connected across the first node and the second node. A first and second bipolar transistors are configured as a differential pair. A first and second FETs are configured in a common-gate configuration. The drain of the first FET comprises a first output of the BiFET VCO circuit, while the drain of the second FET comprises a second output of the BiFET VCO circuit.
摘要翻译：根据一个示例性实施例，VCO核心电路跨越第一节点和第二节点连接。第一变容二极管的阳极连接到第一节点，而第二变容二极管的阳极连接到第二节点，并且第一变容二极管的阴极连接到第二变容二极管的阴极。调谐电压也连接到第一变容二极管的阴极和第二变容二极管的阴极。电感器连接在第一节点和第二节点之间。第一和第二双极晶体管被配置为差分对。第一和第二FET被配置成共栅配置。第一FET的漏极包括BiFET VCO电路的第一输出，而第二FET的漏极包括BiFET VCO电路的第二输出。

50. 发明申请

WO2003067629A3 BAND GAP COMPENSATED HBT 审中-公开
公开(公告)号：WO2003067629A3
公开(公告)日：2003-08-14
申请号：PCT/US2002/038271
申请日：2002-11-27
申请人： NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTOR
发明人： U'REN, Greg, D. , SCHUEGRAF, Klaus, F. , RACANELLI, Marco
IPC分类号： H01L29/06
摘要： The invention provides a heterojunction bipolar transistor in which a base has a concentration of a first material (424) at a first depth (416). The first material impedes the diffusion of a base dopant (402) and causes a change in band gap at the first depth (416) in the base. The base as also a concentration of a second materiel (426). The second material increases at the first depth (416) so as to counteract the change in band gap. The concentration of the second material (426) increases at the first depth (416) by the amount that is required to cause a decrease in band gap to be substantially equal to the increase in band gap that is caused by concentration of the first material (424).

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式