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    • 31. 发明专利
    • Frequency converting circuit, reception circuit, and radio clock
    • 频率转换电路,接收电路和无线电时钟
    • JP2008206010A
    • 2008-09-04
    • JP2007041971
    • 2007-02-22
    • Casio Comput Co Ltdカシオ計算機株式会社
    • SOMEYA KAORU
    • H04B1/26G04G5/00G04R20/10G04R40/02H03D7/00
    • PROBLEM TO BE SOLVED: To stabilize a VCO signal and to obtain an appropriate intermediate frequency signal. SOLUTION: A frequency converting circuit 23 includes an oscillation circuit 30 for outputting, as an oscillation signal, a reference signal or a signal obtained by multiplying the reference signal, a frequency divider 34 for dividing the oscillation signal to generate a local oscillation signal and dividing the oscillation signal to generate a clock signal for controlling a variable filter 38, a mixer 36 for receiving the local oscillation signal and a received signal and mixing them to output a signal having an intermediate frequency, and the variable filter 38 that can change a center frequency depending on the clock signal. A frequency division ratio in the frequency divider is controlled so that the center frequency in the variable filter 38 is substantially equal to the intermediate frequency. COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:为了稳定VCO信号并获得适当的中频信号。 解决方案:频率转换电路23包括:振荡电路30,用于输出作为振荡信号的参考信号或通过乘以参考信号获得的信号;分频器34,用于分频振荡信号以产生本地振荡 信号并分频振荡信号以产生用于控制可变滤波器38的时钟信号,用于接收本地振荡信号的混频器36和接收信号并将它们混合以输出具有中频的信号,以及可变滤波器38,其可以 根据时钟信号改变中心频率。 控制分频器中的分频比使得可变滤波器38中的中心频率基本上等于中频。 版权所有(C)2008,JPO&INPIT