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31. 发明公开

EP1315170A3 Multibit memory device 审中-公开
标题翻译：多位存储设备
公开(公告)号：EP1315170A3
公开(公告)日：2004-07-14
申请号：EP02258092.2
申请日：2002-11-25
申请人： Hewlett-Packard Company
发明人： Sharma, Manish , Tran,Lung T.
IPC分类号： G11C11/56 , G11C11/15
CPC分类号： H01L27/224 , G11C11/005 , G11C11/16 , G11C11/56 , G11C11/5607 , G11C11/5671 , G11C17/16 , G11C2216/26
摘要： A memory device (50) includes memory cells (130, 230) having re-writeable element (134, 234) and a write-once element (136, 236) in series with the re-writeable element (134, 234), the re-writeable element (134, 234) being programmable between a high resistance state and a low resistance state. The write-once element (136, 236) can be an anti-fuse element that is programmable from a high resistance state to a low resistance state, or a fuse element that is programmable from a low resistance state to a high resistance state. The two possible states for the re-writeable element (134, 234) and the two possible states for the write-once element (136, 236) allow the memory cells (130, 230) to store four different bits.
摘要翻译：存储器件（50）包括具有可重写元件（134,234）和与可重写元件（134,234）串联的一次写入元件（136,236）的存储器单元（130,230），所述可重写元件（134,234）可在高电阻状态和低电阻状态之间编程。一次写入元件（136,236）可以是可从高电阻状态编程到低电阻状态的反熔丝元件，或者是可从低电阻状态编程到高电阻状态的熔丝元件。用于可重写元件（134,234）的两种可能状态和用于一次写入元件（136,236）的两种可能状态允许存储器单元（130,230）存储四个不同的位。

32. 发明公开

EP2494450A2 ONE-TIME PROGRAMMABLE MEMORY DEVICE AND METHODS THEREOF 有权转让
标题翻译： ONCE可编程存储器装置及其方法
公开(公告)号：EP2494450A2
公开(公告)日：2012-09-05
申请号：EP10830402.3
申请日：2010-10-19
申请人： Freescale Semiconductor, Inc.
发明人： STRAUSS, Timothy, J. , TAYLOR, Kelly, K.
IPC分类号： G06F13/10 , G11C16/10 , G06F13/14 , G11C16/08
CPC分类号： G11C16/10 , G11C16/22 , G11C16/26 , G11C16/3459 , G11C2216/26
摘要： A portion of a programmable memory device is configured as a one-time programmable (OTP) memory, where in response to a write access to the memory device, a memory controller determines whether the write access is associated with a memory location designated as an OTP memory location. If so, the memory controller performs a read of the memory location, and allows the write access only if each memory cell of the memory location is in an un-programmed state. Thus, only a single write access to an OTP memory location is permitted, and subsequent write attempts are disallowed. Further, to enhance detection of programmed cells, the read of the OTP memory location is performed with a lower read voltage than a read voltage associated with a write access to a non-OTP memory location, thereby improving detection of programmed memory cells in the OTP memory location.

33. 发明公开

EP1918808A3 Storage system 审中-公开
标题翻译：存储系统
公开(公告)号：EP1918808A3
公开(公告)日：2010-07-07
申请号：EP07251777.4
申请日：2007-04-27
申请人： Hitachi, Ltd.
发明人： Fujita, Takahiro, c/o Hitachi, Ltd. , Mannen, Akihiro, c/o Hitachi, Ltd. , Hosouchi, Masaaki, c/o Hitachi, Ltd. , Yagawa, Yuichi, c/o Hitachi, Ltd.
IPC分类号： G06F3/06 , G11C16/22
CPC分类号： G11C16/22 , G06F3/0623 , G06F3/0634 , G06F3/0637 , G06F3/0688 , G11C17/16 , G11C17/18 , G11C2216/26
摘要： A storage system where storage devices themselves have WORM functionality that can be set at any time. The storage system includes storage devices, and a controller for controlling data transmission between the storage devices and an information processor. Each storage device has a storage cell and a fuse at a midpoint on a write control line, and the controller applies a voltage to the fuse to blow it to set WORM for the storage cell.
摘要翻译：存储设备本身具有可以随时设置的WORM功能的存储系统。存储系统包括存储装置和用于控制存储装置与信息处理器之间的数据传输的控制器。每个存储设备在写入控制线的中点具有存储单元和保险丝，并且控制器向保险丝施加电压以将其设置为为存储单元设置WORM。

34. 发明公开

EP1918808A2 Storage system 审中-公开
标题翻译： Speichersystem
公开(公告)号：EP1918808A2
公开(公告)日：2008-05-07
申请号：EP07251777.4
申请日：2007-04-27
申请人： Hitachi, Ltd.
发明人： Fujita, Takahiro, c/o Hitachi, Ltd. , Mannen, Akihiro, c/o Hitachi, Ltd. , Hosouchi, Masaaki, c/o Hitachi, Ltd. , Yagawa, Yuichi, c/o Hitachi, Ltd.
IPC分类号： G06F3/06 , G11C16/22
CPC分类号： G11C16/22 , G06F3/0623 , G06F3/0634 , G06F3/0637 , G06F3/0688 , G11C17/16 , G11C17/18 , G11C2216/26
摘要： A storage system where storage devices themselves have WORM functionality that can be set at any time. The storage system includes storage devices, and a controller for controlling data transmission between the storage devices and an information processor. Each storage device has a storage cell and a fuse at a midpoint on a write control line, and the controller applies a voltage to the fuse to blow it to set WORM for the storage cell.
摘要翻译：存储系统，其中存储设备本身具有可以随时设置的WORM功能。存储系统包括存储装置和用于控制存储装置与信息处理器之间的数据传输的控制器。每个存储设备在写入控制线上的中点具有存储单元和保险丝，并且控制器向保险丝施加电压以对存储单元设置WORM。

35. 发明公开

EP0838826A1 Mémoire non volatile multiniveau modifiable électriquement comportant des moyens de rafraîchissement internes 失效转让
标题翻译： Elektrisch modifizierbarernichtflüchtigerMehrpegelspeicher mit internen Auffrischungsmitteln
公开(公告)号：EP0838826A1
公开(公告)日：1998-04-29
申请号：EP97460043.9
申请日：1997-10-21
申请人： SGS-THOMSON MICROELECTRONICS S.A.
发明人： Yero, Emilio Miguel
IPC分类号： G11C11/56
CPC分类号： G11C16/3418 , G11C11/5621 , G11C16/3431 , G11C2216/26
摘要： L'invention concerne une mémoire non volatile multiniveau modifiable électriquement comportant des moyens de rafraîchissement internes. Selon l'invention, si on considère une mémoire comportant n secteurs, n-1 secteurs seulement sont affectés simultanément au stockage des données et le secteur restant ou secteur de rafraîchissement est utilisé pour recevoir les données dupliquées de l'un desdits n-1 secteurs affectés simultanément au stockage des données. Après chaque duplication, le secteur dupliqué est remplacé par ledit secteur de rafraîchissement et devient lui-même le nouveau secteur de rafraîchissement, de telle sorte que l'ensemble des n secteurs participent tour à tour au rafraîchissement.
摘要翻译：存储器包括连接到行解码器（3）和列解码器（4）的单元的阵列（1）。解码器连接到读写电路（5）。编程电路（7）包括振荡器和电压斜坡发生器。解码器连接到地址寄存器（AD-R）和接口。控制电路（2）包括与可编程组件（4B）协作的存储器刷新组件（2A），可编程组件（4B）选择要刷新的存储器阵列的扇区。在阵列中提供了一个用于存储数据的附加扇区。

36. 发明申请

WO2011059645A2 ONE-TIME PROGRAMMABLE MEMORY DEVICE AND METHODS THEREOF 审中-公开
标题翻译：一次可编程存储器件及其方法
公开(公告)号：WO2011059645A2
公开(公告)日：2011-05-19
申请号：PCT/US2010/053205
申请日：2010-10-19
申请人： FREESCALE SEMICONDUCTOR, INC. , STRAUSS, Timothy, J. , TAYLOR, Kelly, K.
发明人： STRAUSS, Timothy, J. , TAYLOR, Kelly, K.
CPC分类号： G11C16/10 , G11C16/22 , G11C16/26 , G11C16/3459 , G11C2216/26
摘要： A portion of a programmable memory device (104) is configured as a one-time programmable (OTP) memory, where in response to a write access to the memory device, a memory controller (118) determines whether the write access is associated with a memory location designated as an OTP memory location (404). If so, the memory controller performs a read of the memory location (408), and allows the write access only if each memory cell of the memory location is in an un-programmed state (410). Thus, only a single write access to an OTP memory location is permitted, and subsequent write attempts are disallowed. Further, to enhance detection of programmed cells, the read of the OTP memory location is performed with a lower read voltage than a read voltage associated with a write access (407) to a non-OTP memory location, thereby improving detection of programmed memory cells in the OTP memory location.
摘要翻译：可编程存储器件（104）的一部分被配置为一次性可编程（OTP）存储器，其中响应于对存储器件的写入访问，存储器控制器（118）确定写访问是否与指定为OTP存储器位置的存储器位置（404）。如果是，存储器控制器执行存储器位置（408）的读取，并且仅当存储器位置的每个存储器单元处于未编程状态时才允许写访问（410）。因此，只允许对OTP存储器位置的单个写入访问，并且不允许后续写入尝试。此外，为了增强对编程单元的检测，以比与非OTP存储器位置的写访问（407）相关联的读取电压更低的读取电压执行OTP存储器位置的读取，由此改进对编程的存储器单元的检测在OTP内存位置。

37. 发明申请

WO2005053002A3 TWO-COMPONENT, RECTIFYING-JUNCTION MEMORY ELEMENT 审中-公开
标题翻译：双组分，修复连接记忆元件
公开(公告)号：WO2005053002A3
公开(公告)日：2007-10-18
申请号：PCT/US2004039749
申请日：2004-11-26
申请人： UNIV PRINCETON
发明人： SMITH SHAWN , FORREST STEPHEN R
IPC分类号： H01L35/24 , G11C13/00 , G11C13/02 , G11C17/16 , H01L20060101 , H01L27/28 , H01L51/00 , H01L51/05 , H01L51/30
CPC分类号： H01L51/0587 , B82Y10/00 , G11C13/0009 , G11C13/0014 , G11C13/0016 , G11C17/16 , G11C2213/72 , G11C2216/26 , H01L27/285 , H01L51/0037
摘要： Embodiments of the present invention are directed to low complexity, efficient, two-component memory elements for use in low-cost, robust, and reliable WORM memories. The memory element of one embodiment is an organic-on-inorganic heterojunction diode comprising an organic-polymer layer joined to a doped, inorganic semiconductor layer. The organic polymer layer serves both as one later of a two-later, semiconductor-based diode, as well as a fuse. Application of a voltage greater than a threshold WRITE voltage for a period of time greater than a threshold time interval for a WRITE-voltage pulse irreversibly and dramatically increases the resistivity of the organic polymer layer. The memory element that represents one embodiment of the present invention is more easily manufactured than previously described, separate-fuse-and-diode memory elements, and has the desirable characteristics of being switchable at lower voltages and with significantly shorter-duration WRITE-voltage pulses than the previously described memory elements.
摘要翻译：本发明的实施例涉及用于低成本，稳健和可靠的WORM存储器的低复杂度，高效率的双分量存储器元件。一个实施方案的存储元件是无机异源结二极管，其包含连接到掺杂的无机半导体层的有机聚合物层。有机聚合物层同时用作两个以后的半导体二极管以及一个保险丝。对于写电压脉冲施加大于阈值写入电压的时间大于阈值时间间隔的时间段，并且显着增加有机聚合物层的电阻率。代表本发明的一个实施例的存储元件比先前描述的更容易制造，分离的熔丝和二极管存储元件，并且具有可在较低电压下切换并具有显着更短持续时间的写电压脉冲的期望特性比之前描述的存储器元件。

38. 发明申请

WO2006044203A2 FLEXIBLE OTP SECTOR PROTECTION ARCHITECTURE FOR FLASH MEMORIES 审中-公开
标题翻译：闪存存储器的灵活OTP部门保护架构
公开(公告)号：WO2006044203A2
公开(公告)日：2006-04-27
申请号：PCT/US2005/035788
申请日：2005-10-04
申请人： ATMEL CORPORATION , REGGIORI, Riccardo, Riva , BEDARIDA, Lorenzo , ODDONE, Georgia , CASER, Fabio, Tassan
发明人： REGGIORI, Riccardo, Riva , BEDARIDA, Lorenzo , ODDONE, Georgia , CASER, Fabio, Tassan
IPC分类号： G11C16/04
CPC分类号： G11C16/22 , G11C2216/26
摘要： A method and system for protecting a memory having a plurality of blocks from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells and OTP cell logic coupled with the OTP cells. An OTP cell of the plurality of OTP cells corresponds to a portion of a block of the plurality of blocks. The OTP cell allows modification of the portion of the block when the OTP cell is in a first state and permanently prevents modification of the portion of the block when the OTP cell is in a second state. The OTP cell logic uses the plurality of OTP cells to select the portion of the block as corresponding to the OTP cell. This portion of the block is write protected when the OTP cell is placed in the second state.
摘要翻译：公开了一种用于保护具有多个块的存储器不被修改的方法和系统。该方法和系统包括提供与OTP单元耦合的多个一次可编程（OTP）单元和OTP单元逻辑。多个OTP单元的OTP单元对应于多个块的块的一部分。当OTP小区处于第一状态时，OTP小区允许修改块的部分，并且当OTP小区处于第二状态时永久地防止修改块的部分。 OTP单元逻辑使用多个OTP单元来选择与OTP单元相对应的块的该部分。当OTP单元处于第二状态时，块的这一部分是写保护的。

39. 发明公开

EP2494450A4 ONE-TIME PROGRAMMABLE MEMORY DEVICE AND METHODS THEREOF 有权转让
标题翻译： VERFAHRENDAFÜR的EINMAL PROGRAMMIBARE SPEICHERVORRICHTUNG
公开(公告)号：EP2494450A4
公开(公告)日：2015-08-19
申请号：EP10830402
申请日：2010-10-19
申请人： FREESCALE SEMICONDUCTOR INC
发明人： STRAUSS TIMOTHY J , TAYLOR KELLY K
IPC分类号： G06F13/10 , G06F13/14 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/26 , G11C16/34
CPC分类号： G11C16/10 , G11C16/22 , G11C16/26 , G11C16/3459 , G11C2216/26
摘要： A portion of a programmable memory device is configured as a one-time programmable (OTP) memory, where in response to a write access to the memory device, a memory controller determines whether the write access is associated with a memory location designated as an OTP memory location. If so, the memory controller performs a read of the memory location, and allows the write access only if each memory cell of the memory location is in an un-programmed state. Thus, only a single write access to an OTP memory location is permitted, and subsequent write attempts are disallowed. Further, to enhance detection of programmed cells, the read of the OTP memory location is performed with a lower read voltage than a read voltage associated with a write access to a non-OTP memory location, thereby improving detection of programmed memory cells in the OTP memory location.
摘要翻译：可编程存储器件的一部分被配置为一次性可编程（OTP）存储器，其中响应于对存储器件的写入访问，存储器控制器确定写访问是否与指定为OTP的存储器位置相关联内存位置。如果是这样，则存储器控制器执行对存储器位置的读取，并且仅当存储器位置的每个存储器单元处于非编程状态时才允许写访问。因此，只允许对OTP存储器位置的单个写入访问，并且不允许后续的写入尝试。此外，为了增强对编程单元的检测，OTP存储器位置的读取以比与非OTP存储器位置的写入访问相关联的读取电压更低的读取电压来执行，从而改进对OTP中的编程存储器单元的检测内存位置。

40. 发明公开

EP2823485A1 FLASH MEMORY WITH INTEGRATED ROM MEMORY CELLS 无效
标题翻译：具有集成ROM存储器单元闪存
公开(公告)号：EP2823485A1
公开(公告)日：2015-01-14
申请号：EP13711498.9
申请日：2013-03-04
申请人： Medtronic Inc.
发明人： WALSH, Kevin, K. , PATTERSON, Paul, B. , BENTON, Glen, W. , WILKINSON, Jeffrey, D.
IPC分类号： G11C16/04 , G11C17/12
CPC分类号： G11C16/04 , G11C17/12 , G11C2216/26
摘要： Memory array for storing a plurality of data bits. The memory array has flash memory cells, ROM memory cells addressing circuitry. The addressing circuitry is operatively coupled to both the plurality of flash memory cells and the plurality of ROM memory cells, the addressing circuitry being configured to address both the plurality of flash memory cells and the plurality of ROM memory cells.

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