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31. 发明公开

EP1418500A2 Method and apparatus to adapt the clock rate of a programmable coprocessor for optimal performance and power dissipation 审中-公开
标题翻译： Annordnung方法和调整的可编程协处理器，以获得最佳的性能和功耗的时钟速率
公开(公告)号：EP1418500A2
公开(公告)日：2004-05-12
申请号：EP03256838.8
申请日：2003-10-29
申请人： STMicroelectronics, Inc.
发明人： Rizzo, Davide , Colavin, Osvaldo
IPC分类号： G06F9/45 , G06F1/32
CPC分类号： G06F8/4432 , G06F1/08 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D10/41
摘要： A coprocessor executing one among a set of candidate kernel loops within an application operates at the minimal clock frequency satisfying schedule constraints imposed by the compiler and data bandwidth constraints. The optimal clock frequency is statically determined by the compiler and enforced at runtime by software-controlled clock circuitry. Power dissipation savings and optimal resource usage are therefore achieved by the adaptation at runtime of the coprocessor clock rate for each of the various kernel loop implementations.

32. 发明申请

WO2017012845A1 COMPUTER SYSTEM AND METHOD FOR MULTI-PROCESSOR COMMUNICATION 审中-公开
标题翻译：用于多处理器通信的计算机系统和方法
公开(公告)号：WO2017012845A1
公开(公告)日：2017-01-26
申请号：PCT/EP2016/065652
申请日：2016-07-04
申请人： KARLSRUHER INSTITUT FÜR TECHNOLOGIE
发明人： MEYER, Johannes , OEY, Oliver , STRIPF, Timo , BECKER, Jürgen
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F8/433 , G06F8/4432 , G06F8/4434 , G06F8/4441 , G06F8/456 , G06F8/457 , G06F8/52 , G06F9/445
摘要： A compiler system (160), computer-implemented method and computer program product for optimizing a program for multi-processor system execution. The compiler includes an interface component (170) configured to load from a storage component (110) program code (111) to be executed by one or more processors (P1 to Pn) of a multi-processor system (190). Through the interface one or more optimized program codes (111-1 to 111-n) are provided to the storage component (110) wherein each optimized program code is configured to be executed by a particular processor of the one or more processors (P1 to Pn). The compiler further includes a static analysis component (120) configured to generate from the program code (111) a control flow graph (300, 400, 500) representing all paths that can be traversed through the execution of the respective program. It determines data dependencies (321, 421, 422, 521, 522, 523, 524) within the program code (111), and further determines all basic blocks of the control flow graph providing potential insertion positions along paths where communication statements can be inserted to enable data flow between different processors at runtime. An evaluation function component of the compiler is configured to evaluate each potential insertion position with regards to its impact on program execution on the multi-processor system (190) at runtime by using a predefined execution evaluation function. A code modification component (150) of the compiler is configured to obtain the one or more optimized program codes (111-1 to 111-n) by inserting coupled send and receive communication instructions statements in each relevant path of the control flow graph at one or more insertion positions wherein each insertion position has an evaluation value which indicates optimal runtime execution for the program when executed on the multi-processor system (190).
摘要翻译：编译器系统（160），用于优化用于多处理器系统执行的程序的计算机实现的方法和计算机程序产品。编译器包括被配置为从要由多处理器系统（190）的一个或多个处理器（P1至Pn）执行的存储组件（110）程序代码（111）加载的接口组件（170）。通过接口，将一个或多个优化的程序代码（111-1至111-n）提供给存储组件（110），其中每个优化的程序代码被配置为由一个或多个处理器（P1到 PN）。编译器还包括静态分析组件（120），其被配置为从程序代码（111）生成表示通过执行相应程序可以遍历的所有路径的控制流程图（300,400,500）。它确定程序代码（111）内的数据相关性（321,421,422,521,522,523,524），并且进一步确定控制流图的所有基本块，其提供沿着可以插入通信语句的路径的潜在插入位置以在运行时启用不同处理器之间的数据流。配置编译器的评估功能组件，用于通过使用预定义的执行评估功能来评估在运行时通过多处理器系统（190）对程序执行的影响的每个潜在的插入位置。编译器的代码修改组件（150）被配置为通过在一个控制流程图的每个相关路径中插入耦合的发送和接收通信指令语句来获得一个或多个优化的程序代码（111-1至111-n）或更多的插入位置，其中每个插入位置具有评估值，其在多处理器系统（190）上执行时指示程序的最佳运行时执行。

33. 发明申请

WO2011085333A1 DOMAIN SPECIFIC LANGUAGE, COMPILER AND JIT FOR DYNAMIC POWER MANAGEMENT 审中-公开
标题翻译：特定语言，编译器和动态电源管理
公开(公告)号：WO2011085333A1
公开(公告)日：2011-07-14
申请号：PCT/US2011/020714
申请日：2011-01-10
申请人： QUALCOMM INCORPORATED , FRANTZ, Andrew J. , GARGASH, Norman S. , ULMER, Tracy A.
发明人： FRANTZ, Andrew J. , GARGASH, Norman S. , ULMER, Tracy A.
IPC分类号： G06F1/32 , G06F9/45
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/3296 , G06F8/41 , G06F8/4432 , Y02D10/171 , Y02D10/172 , Y02D10/41
摘要： The aspects enable a computing device or microprocessor to determine a low-power mode that maximizes system power savings by placing selected resources in a low power mode while continuing to function reliably, depending upon the resources not in use, acceptable system latencies, dynamic operating conditions (e.g., temperature), expected idle time, and the unique electrical characteristics of the particular device. The various aspects provide mechanisms and methods for compiling a plurality of low power resource modes to generate one or more synthetic low power resources from which can be selected an optimal low-power mode configuration made up of a set of selected synthetic low power resources.
摘要翻译：这些方面使得计算设备或微处理器能够根据不使用的资源，可接受的系统延迟，动态操作条件来确定通过将所选择的资源置于低功率模式同时继续可靠地运行来最大化系统功率节省的低功率模式（例如，温度），预期的空闲时间和特定设备的独特电气特性。各个方面提供了用于编译多个低功率资源模式以产生一个或多个合成低功率资源的机制和方法，从中可以选择由一组选定的合成低功率资源组成的最佳低功率模式配置。

34. 发明申请

WO2004046921A3 COST-AWARE DESIGN-TIME/RUN-TIME MEMORY MANAGEMENT METHODS AND APPARATUS 审中-公开
标题翻译： COST-AWARE设计时间/运行时记忆管理方法和设备
公开(公告)号：WO2004046921A3
公开(公告)日：2005-05-06
申请号：PCT/BE0300202
申请日：2003-11-18
申请人： IMEC INTER UNI MICRO ELECTR , MARCHAL PAUL , GOMEZ JOSE IGNACIO , BRUNI DAVIDE , CATTHOOR FRANCKY
发明人： MARCHAL PAUL , GOMEZ JOSE IGNACIO , BRUNI DAVIDE , CATTHOOR FRANCKY
IPC分类号： G06F9/45
CPC分类号： G06F8/4432 , G06F8/4442 , Y02D10/41
摘要： Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g. multi-banked memories in an essentially digital system as well as methods, apparatus and software products for runtime memory management techniques of such a such a system. Memory assignment techniques are described for assigning data to a hierarchical memory particularly for multi-tasked applications where data of dynamically crated/deleted tasks is allocated at run-time. The energy consumption of hierarchical memories such as multi-banked memories depends largely on how data is assigned to the memory banks. Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g. multi-banked memories in an essentially digital system which improve a cost function such as energy consumption.
摘要翻译：描述了分层存储器的设计时数据分配技术的方法，装置和软件产品，例如。基本数字系统中的多存储存储器以及用于这种系统的运行时存储器管理技术的方法，装置和软件产品。描述了用于将数据分配给分层存储器的内存分配技术，特别是对于在运行时分配动态封装/删除任务的数据的多任务应用程序。分层存储器（诸如多存储器存储器）的能量消耗在很大程度上取决于数据如何被分配给存储器组。描述了分层存储器的设计时数据分配技术的方法，装置和软件产品，例如。在本质上数字系统中的多存储器，其改善诸如能量消耗的成本功能。

35. 发明公开

KR1020040076197A 마이크로프로세서의 전력 소비를 감소시키는 방법 및 머신코드 구축기 失效
标题翻译：降低机器代码制造商在微处理器和机器代码建筑物上耗电的方法
公开(公告)号：KR1020040076197A
公开(公告)日：2004-08-31
申请号：KR1020030100394
申请日：2003-12-30
申请人： 인터내셔널 비지네스 머신즈 코포레이션
发明人： 쿠크토마스이 , 고베트이안알 , 김수환 , 코소노키스테펜브이 , 샌든피터에이
IPC分类号： G06F1/32
CPC分类号： G06F8/4432 , Y02D10/41
摘要： PURPOSE: A method for reducing power consumption derived from a machine code builder on a microprocessor and the machine code builder are provided to reduce the power consumption by maximizing a time that resource is not required, as a machine code is built from a pre-executable code. CONSTITUTION: The microprocessor executes an instruction of the machine code(28). The machine code builder(22) includes a reader unit(32), a builder unit(34), a profiler unit(36), a re-energizing simulation unit(38), a code block executing condition unit(40), a function syntax saver unit(42), and a performance optimizer/profiler(50). The performance optimizer/profiler builds the machine code so as to increase performance.
摘要翻译：目的：提供一种降低从微处理器和机器代码构建器上的机器代码生成器导出的功耗的方法，以便通过最大化不需要该资源的时间来降低功耗，因为机器代码是由预执行码。构成：微处理器执行机器代码（28）的指令。机器代码生成器（22）包括读取器单元（32），构建器单元（34），分析器单元（36），再通电模拟单元（38），代码块执行条件单元（40），功能语法保护单元（42）和性能优化器/剖析器（50）。性能优化器/分析器构建机器代码，以提高性能。

36. 发明授权

KR100582378B1 마이크로프로세서의 전력 소비를 감소시키는 방법 및 머신코드 구축기 失效
标题翻译：机器代码制造商降低功耗
公开(公告)号：KR100582378B1
公开(公告)日：2006-05-22
申请号：KR1020030100394
申请日：2003-12-30
申请人： 인터내셔널 비지네스 머신즈 코포레이션
发明人： 쿠크토마스이 , 고베트이안알 , 김수환 , 코소노키스테펜브이 , 샌든피터에이
IPC分类号： G06F1/32
CPC分类号： G06F8/4432 , Y02D10/41
摘要： 개선된 소프트웨어 제어형 프로그램 관리를 제공하는 머신 코드 구축기가 개시된다. 머신 코드 구축기는 실행전 코드를 독출하고, 실행전 코드로부터 머신 코드를 구축하여 자원이 요청되지 않는 기간을 최대화한다. 사용되지 않는 자원은 사용자 정의되거나 구축기가 실행전 코드를 분석해서 어느 자원이 요청되지 않을지를 판정할 수 있다. 구축기는 머신 코드를 재편성하여 특정 자원이 사용되지 않는 시간을 최대화한다. 성능의 손실을 방지하기 위해 자원의 전력 재인가 동안 자원 에뮬레이션 코드가 수행되게 하는 메커니즘이 제공되기도 한다.

37. 发明授权

EP2241969B1 Program and data annotation for hardware customization and energy optimization 有权
公开(公告)号：EP2241969B1
公开(公告)日：2018-08-29
申请号：EP10154705.7
申请日：2010-02-25
申请人： Empire Technology Development LLC
发明人： Potkonjak, Miodrag
IPC分类号： G06F9/44 , G06F1/32 , G06F8/41
CPC分类号： G06F1/3234 , G06F8/4432 , Y02D10/41
摘要： Technologies are generally described herein for supporting program and data annotation for hardware customization and energy optimization. A code block to be annotated may be examined and a hardware customization may be determined to support a specified quality of service level for executing the code block with reduced energy expenditure. Annotations may be determined as associated with the determined hardware customization. An annotation may be provided to indicate using the hardware customization while executing the code block. Examining the code block may include one or more of performing a symbolic analysis, performing an empirical observation of an execution of the code block, performing a statistical analysis, or any combination thereof. A data block to be annotated may also be examined. One or more additional annotations to be associated with the data block may be determined.

38. 发明公开

EP2731008A1 Resource contention in multiple cores 有权
标题翻译： Ressourcenkonflikte在mehreren Kernen
公开(公告)号：EP2731008A1
公开(公告)日：2014-05-14
申请号：EP12192302.3
申请日：2012-11-12
申请人： FUJITSU LIMITED
发明人： Li, Michael
IPC分类号： G06F9/45
CPC分类号： G06F8/458 , G06F8/4432 , G06F9/30076 , G06F9/522 , G06F2209/522 , Y02D10/41
摘要： A processing method of a software application on a computer system having a plurality of processing cores for independently executing instructions, some common hardware resources in the system being shared among the cores. Source code for the application is developed by a programmer (S10). The source code of the application is compiled (S14) to obtain a sequence of executable instructions for the cores by analysing the source code, identifying at least one resource contention among the cores predicted to result from execution of instructions by the cores, and inserting an additional instruction in the sequence for at least identifying the resource contention. Then the compiled application is run (S18) by executing the sequence of executable instructions by said cores to perform operations in said computer system, these operations including action to mitigate the resource contention in response to executing said additional instruction. Results of execution can be collected and fed back to the development process. The method allows possible resource contention to be indicated automatically as part of the compilation process and mitigated, if necessary, at run-time.
摘要翻译：一种具有用于独立执行指令的多个处理核的计算机系统上的软件应用的处理方法，所述系统中的一些常见的硬件资源在所述核之间共享。应用程序的源代码由程序员开发（S10）。编译应用程序的源代码（S14），以通过分析源代码来识别核心的可执行指令序列，识别由核心执行指令而产生的核心中的至少一个资源争用，并且插入序列中的附加指令至少识别资源争用。然后，通过执行所述核心的可执行指令序列来运行编译的应用程序（S18），以在所述计算机系统中执行操作，这些操作包括响应于执行所述附加指令而减轻资源争用的动作。执行结果可以收集并反馈给开发过程。该方法允许可能的资源争用被自动指示为编译过程的一部分，并在必要时在运行时缓解。

39. 发明公开

EP2202638A4 TRANSLATING DEVICE, TRANSLATING METHOD AND TRANSLATING PROGRAM, AND PROCESSOR CORE CONTROL METHOD AND PROCESSOR 审中-公开
标题翻译：翻译装置，翻译方法及翻译程序和处理器核控制方法和处理器
公开(公告)号：EP2202638A4
公开(公告)日：2011-12-14
申请号：EP07805864
申请日：2007-09-21
申请人： FUJITSU LTD
发明人： YAMASHITA KOICHIRO
IPC分类号： G06F9/45 , G06F1/04 , G06F1/32 , G06F9/50
CPC分类号： G06F8/452 , G06F8/4432 , G06F9/50 , Y02D10/22 , Y02D10/41
摘要： When parallel processing is performed by a system configured by a plurality of processors and a multicore processor chip, power control code can be reduced by dynamically changing the number of processors for performing the parallel processing and an operation clock of each processor. A translation device includes: a parallel loop processing detection unit configured to detect from the source code a loop processing code for execution of an internal processing operation for a given number of repeating times, and an independent parallel loop processing code in the internal processing operation performed for each repetition to be concurrently processed; and a dynamic parallel conversion unit configured to generate a control core code for control of the number of repeating times in the parallel loop processing code and a parallel processing code for changing the number of repeating times corresponding to the control from the control core code. The technology also relates to a translating method, a translating program, a control method for a processor core, and a processor.

40. 发明公开

EP2290538A3 Method and device for reducing power consumption in application specific instruction set processors 审中-公开
标题翻译：用于减少应用专用指令集的处理器的功耗的方法和设备
公开(公告)号：EP2290538A3
公开(公告)日：2011-06-22
申请号：EP10174072.8
申请日：2010-08-26
申请人： IMEC , Katholieke Universiteit Leuven, K.U. Leuven R&D
发明人： Raghavan, Praveen , Novo Bruna, David , Catthoor, Francky , Krithikakou, Angeliki
IPC分类号： G06F9/45
CPC分类号： G06F8/4432 , G06F8/4441 , Y02D10/41
摘要： The present invention provides a compile or pre-compile method and a device for converting first program code into second program code, such that the second program code has an improved execution on a targeted programmable platform. The method according to embodiments of the present invention comprises
grouping operations on data for joint execution on a functional unit of the targeted platform, scheduling operations on data in time, and
assigning operations to an appropriate functional unit of the targeted platform,
wherein detailed word length information is used in at least one of the grouping, scheduling or assigning operations, rather than the typically used approximations like powers of two.

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