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31. 发明授权

US08769451B2 Semiconductor device design method, system and computer program product 有权
标题翻译：半导体器件设计方法，系统和计算机程序产品
公开(公告)号：US08769451B2
公开(公告)日：2014-07-01
申请号：US13547251
申请日：2012-07-12
申请人： Ping-Hung Yuh , Cheng-I Huang , Chung-Hsing Wang
发明人： Ping-Hung Yuh , Cheng-I Huang , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5081
摘要： In a semiconductor device design method performed by at least one processor, at least one first parasitic parameter between electrical components inside a region of a layout of a semiconductor device and at least one second parasitic parameter between electrical components outside the region of the layout are extracted by different tools. The extracted parasitic parameters are incorporated into the layout.
摘要翻译：在由至少一个处理器执行的半导体器件设计方法中，提取在半导体器件的布局的区域内的电气元件之间的至少一个第一寄生参数和在布局区域之外的电气元件之间的至少一个第二寄生参数通过不同的工具。提取的寄生参数被并入到布局中。

32. 发明授权

US08694945B2 Automatic place and route method for electromigration tolerant power distribution 有权
标题翻译：用于电迁移容量配电的自动放置和布线方法
公开(公告)号：US08694945B2
公开(公告)日：2014-04-08
申请号：US13331329
申请日：2011-12-20
申请人： Chung-Hsing Wang , King-Ho Tam , Huang-Yu Chen
发明人： Chung-Hsing Wang , King-Ho Tam , Huang-Yu Chen
IPC分类号： G06F17/50 , H01L23/498
CPC分类号： H01L23/5286 , G06F17/5072 , G06F17/5077 , G06F2217/78 , H01L2027/11881 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and route tool constructs a local power network having multi-level power rails. The multi-level power rails have interleaved segments of vertically adjacent metal layers, wherein each interleaved segment is shorter than a predetermined characteristic length corresponding to a Blech length. By limiting the length of the interleaved metallization segments, electromigration within the multi-level power rails is alleviated, allowing for the maximum current density requirement (Jmax) for mean time to failures (MTTF) to be increased.
摘要翻译：本公开涉及通过自动位置和路由（APR）方法产生的电迁移容限配电网络。在一些实施例中，自动放置和路由工具构建具有多级电源轨的本地电力网络。多级电源轨具有交错的垂直相邻金属层的段，其中每个交错段短于对应于Blech长度的预定特征长度。通过限制交错金属化段的长度，多级电力轨道内的电迁移得到缓解，允许增加平均故障时间（MTTF）的最大电流密度要求（Jmax）。

33. 发明授权

US08601409B1 Compression method and system for use with multi-patterning 有权
公开(公告)号：US08601409B1
公开(公告)日：2013-12-03
申请号：US13547107
申请日：2012-07-12
申请人： Huang-Yu Chen , Chin-Hsiung Hsu , Wen-Hao Chen , Chung-Hsing Wang
发明人： Huang-Yu Chen , Chin-Hsiung Hsu , Wen-Hao Chen , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G03F1/70 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.

34. 发明授权

US08539396B2 Stitch and trim methods for double patterning compliant standard cell design 有权
标题翻译：针对符合标准单元设计的双图案的针迹和修剪方法
公开(公告)号：US08539396B2
公开(公告)日：2013-09-17
申请号：US13415997
申请日：2012-03-09
申请人： Chin-Hsiung Hsu , Huang-Yu Chen , Chung-Hsing Wang
发明人： Chin-Hsiung Hsu , Huang-Yu Chen , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5072 , G06F2217/78
摘要： A method for creating double patterning compliant integrated circuit layouts is disclosed. The method allows patterns to be assigned to different masks and stitched together during lithography. The method also allows portions of the pattern to be removed after the process.
摘要翻译：公开了一种用于产生双重图案化的集成电路布局的方法。该方法允许在光刻期间将图案分配给不同的掩模并缝合在一起。该方法还允许在处理之后去除图案的部分。

35. 发明申请

US20130154128A1 Automatic Place and Route Method for Electromigration Tolerant Power Distribution 有权
标题翻译：自动放置和路由方法的电迁移容错配电
公开(公告)号：US20130154128A1
公开(公告)日：2013-06-20
申请号：US13331329
申请日：2011-12-20
申请人： Chung-Hsing Wang , King-Ho Tam , Huang-Yu Chen
发明人： Chung-Hsing Wang , King-Ho Tam , Huang-Yu Chen
IPC分类号： H01L23/498 , G06F17/50
CPC分类号： H01L23/5286 , G06F17/5072 , G06F17/5077 , G06F2217/78 , H01L2027/11881 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and route tool constructs a local power network having multi-level power rails. The multi-level power rails have interleaved segments of vertically adjacent metal layers, wherein each interleaved segment is shorter than a predetermined characteristic length corresponding to a Blech length. By limiting the length of the interleaved metallization segments, electromigration within the multi-level power rails is alleviated, allowing for the maximum current density requirement (Jmax) for mean time to failures (MTTF) to be increased.
摘要翻译：本公开涉及通过自动位置和路由（APR）方法产生的电迁移容限配电网络。在一些实施例中，自动放置和路由工具构建具有多级电源轨的本地电力网络。多级电源轨具有交错的垂直相邻金属层的段，其中每个交错段短于对应于Blech长度的预定特征长度。通过限制交错金属化段的长度，多级电力轨道内的电迁移得到缓解，允许增加平均故障时间（MTTF）的最大电流密度要求（Jmax）。

36. 发明授权

US08252489B2 Mask-shift-aware RC extraction for double patterning design 有权
标题翻译：面罩移位感知RC提取双图案设计
公开(公告)号：US08252489B2
公开(公告)日：2012-08-28
申请号：US13167905
申请日：2011-06-24
申请人： Ke-Ying Su , Chung-Hsing Wang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Ke-Ying Su , Chung-Hsing Wang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G03F9/00 , G06F17/50
CPC分类号： G06F17/5081 , G03F1/70 , G03F7/70433 , G03F7/70466 , G06F17/5036
摘要： A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift. The step of simulating the worst-case performance includes calculating capacitance values corresponding to mask shifts, and the capacitance values are calculated using a high-order equation or a piecewise equation.
摘要翻译：一种方法包括提供集成电路设计的布局，以及从布局生成多个双重图案化分解，多个双重图案化分解中的每一个包括分离到第一掩模的图案和双图案掩模组的第二掩模。确定第一和第二掩模之间的最大偏移，其中最大偏移是用于在晶片上实现布局的制造过程中的最大预期掩模移位。对于多个双重图案化分解中的每一个，使用由最大偏移限定的范围内的掩模移位来模拟最坏情况的性能值。模拟最坏情况性能的步骤包括计算与掩模移位相对应的电容值，并且使用高阶方程或分段方程计算电容值。

37. 发明申请

US20090278251A1 Pad Structure for 3D Integrated Circuit 有权
标题翻译： 3D集成电路的焊盘结构
公开(公告)号：US20090278251A1
公开(公告)日：2009-11-12
申请号：US12119255
申请日：2008-05-12
申请人： Chih-Sheng Tsai , Chung-Hsing Wang
发明人： Chih-Sheng Tsai , Chung-Hsing Wang
IPC分类号： H01L23/12 , H01L23/48 , H03K19/094
CPC分类号： H01L25/0657 , H01L23/481 , H01L24/05 , H01L24/12 , H01L2224/0401 , H01L2224/05093 , H01L2224/05096 , H01L2224/0558 , H01L2224/05624 , H01L2224/1134 , H01L2224/13025 , H01L2224/13099 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00013 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/01087 , H01L2924/14 , H01L2924/00014
摘要： This invention discloses an I/O pad structure in an integrated circuit (IC) which comprises a first vertical region in the IC including a top metal layer and one or more semiconductor devices formed thereunder, the top metal layer in the first vertical region serving as a first pad, the semiconductor devices being electrically connected to the first pad, and a second vertical region in the IC next to the first vertical region including the top metal layer and one or more through-silicon-vias (TSVs) formed thereunder, the top metal layer in the second vertical region serving as a second pad, and no semiconductor devices being formed beneath the second pad, the TSVs being electrically connected to the second pad, wherein the first and the second pad are electrically connected through at least one metal layer.
摘要翻译：本发明公开了一种集成电路（IC）中的I / O焊盘结构，其包括IC中的第一垂直区域，其包括顶部金属层和形成在其上的一个或多个半导体器件，第一垂直区域中的顶部金属层用作第一焊盘，半导体器件电连接到第一焊盘，以及IC中的第二垂直区域，紧邻包括顶部金属层的第一垂直区域和在其下形成的一个或多个穿硅通孔（TSV），所述第二垂直区域中的顶部金属层用作第二焊盘，并且在所述第二焊盘下方没有形成半导体器件，所述TSV电连接到所述第二焊盘，其中所述第一焊盘和所述第二焊盘通过至少一种金属层。

38. 发明授权

US08601408B2 Method and system for replacing a pattern in a layout 有权
公开(公告)号：US08601408B2
公开(公告)日：2013-12-03
申请号：US13269757
申请日：2011-10-10
申请人： Huang-Yu Chen , Yuan-Te Hou , Chung-Min Fu , Chung-Hsing Wang , Wen-Hao Chen , Yi-Kan Cheng
发明人： Huang-Yu Chen , Yuan-Te Hou , Chung-Min Fu , Chung-Hsing Wang , Wen-Hao Chen , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

39. 发明授权

US08499274B2 Computer implemented system and method for leakage calculation 有权
标题翻译：计算机实现系统和泄漏计算方法
公开(公告)号：US08499274B2
公开(公告)日：2013-07-30
申请号：US13403289
申请日：2012-02-23
申请人： Chien-Ju Chao , Jerry Chang-Jui Kao , King-Ho Tam , Chung-Hsing Wang , Huan Chi Tseng
发明人： Chien-Ju Chao , Jerry Chang-Jui Kao , King-Ho Tam , Chung-Hsing Wang , Huan Chi Tseng
IPC分类号： G06F17/50 , G06F9/455 , G06G7/48
CPC分类号： G06F17/5022
摘要： A tool includes one or more machine readable storage mediums encoded with data. The data include a list of standard cells included in an integrated circuit (IC) design The data include a nominal leakage value approximating a respective median leakage value for each of the plurality of standard cells at a predetermined temperature and voltage. The data include at least one table including adjustment factors for calculating leakage based on voltage, temperature and process variations. The table includes a respective statistical scaling factor, for computing a mean leakage corresponding to a given median leakage. A processor is programmed to calculate and output a total IC leakage for the IC design at an input voltage and input temperature, based on the list, the nominal leakage values, the input voltage, the input temperature and at least one of the adjustment factors.
摘要翻译：工具包括用数据编码的一个或多个机器可读存储介质。数据包括集成电路（IC）设计中包括的标准单元的列表。数据包括在预定温度和电压下接近多个标准单元中的每一个的相应中值泄漏值的标称泄漏值。数据包括至少一个表，其中包括基于电压，温度和过程变化来计算泄漏的调整因子。该表包括相应的统计缩放因子，用于计算对应于给定中位泄漏的平均泄漏。处理器被编程为基于列表，标称泄漏值，输入电压，输入温度和至少一个调整因子来计算并输出IC设计中的IC设计的总IC泄漏，输入电压和输入温度。

40. 发明申请

US20130139120A1 COMPUTER IMPLEMENTED SYSTEM AND METHOD FOR LEAKAGE CALCULATION 有权
标题翻译：计算机实现系统和泄漏计算方法
公开(公告)号：US20130139120A1
公开(公告)日：2013-05-30
申请号：US13403289
申请日：2012-02-23
申请人： Chien-Ju Chao , Jerry Chang-Jui Kao , King-Ho Tam , Chung-Hsing Wang , Huan Chi Tseng
发明人： Chien-Ju Chao , Jerry Chang-Jui Kao , King-Ho Tam , Chung-Hsing Wang , Huan Chi Tseng
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A tool includes one or more machine readable storage mediums encoded with data. The data include a list of standard cells included in an integrated circuit (IC) design The data include a nominal leakage value approximating a respective median leakage value for each of the plurality of standard cells at a predetermined temperature and voltage. The data include at least one table including adjustment factors for calculating leakage based on voltage, temperature and process variations. The table includes a respective statistical scaling factor, for computing a mean leakage corresponding to a given median leakage. A processor is programmed to calculate and output a total IC leakage for the IC design at an input voltage and input temperature, based on the list, the nominal leakage values, the input voltage, the input temperature and at least one of the adjustment factors.
摘要翻译：工具包括用数据编码的一个或多个机器可读存储介质。数据包括集成电路（IC）设计中包括的标准单元的列表。数据包括在预定温度和电压下接近多个标准单元中的每一个的相应中值泄漏值的标称泄漏值。数据包括至少一个表，其中包括基于电压，温度和过程变化来计算泄漏的调整因子。该表包括相应的统计缩放因子，用于计算对应于给定中位泄漏的平均泄漏。处理器被编程为基于列表，标称泄漏值，输入电压，输入温度和至少一个调整因子来计算并输出IC设计中的IC设计的总IC泄漏，输入电压和输入温度。

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